IO Buffers Design - SMDP-C2SD

1 INTRODUCTION TO IO Buffers (PADS) Design IN IC COMMUNICATIONS VENKATA REDDY KOLAGATLA Senior Technical Officer , CDAC Bangalore Topics going to be covered Basic Block diagram of IO communication & Introduction to IOs Buffered Vs Unbuffered Basics RC Circuits Drive Strength Requirements Output buffer/Driver/Transmitter Design Signal Integrity Analysis Transmission Lines Basic input buffer/Receiver Design A new project Design methodology Further study on IOs Questions/References/Appendix Basic block diagram of IO Communication & Introduction to IOs Generic Diagram of IO communication (IC to IC Communication)

2 Printed Wiring Board Buffers package package Receiver Data generator CMOS IC1 CMOS IC2 Introduction to IOs Input/Output (IO) circuits enable a chip to communicate with the external world. They are placed at the periphery of a chip and provide an interface between the chip and the external world. As the internal circuitry grows in speed and efficiency, it processes data faster. Matching IO circuits, in terms of speed and bandwidth, are critical to make sure that the processing power and efficiency of the internal circuitry or the core circuitry is best used.

3 The electrical signal outside the chip is unknown and possibly unsafe for the internal circuitry. IOs help isolate the chip from such an environment and helps convert the external signal to a form where the internal circuit can process it. Why I/O Buffers The term buffer is used alternately for IO , since IOs does not perform any logic operation on the signals!! Properly drive different loads Get clean (less noisy) signal from incoming noisy signal Provide proper interface between ICs with different signal levels Isolate internal circuit from external effects Translate incoming/outgoing signal level to the required internal/external signal level Types of IOs Depending on the type of application or direction of data flow, IOs can be classified into different types.

4 Input Output (2 states or 3 states) Bi directional Input Buffer The input buffer passes external data to the core. It performs the level conversion from the external voltage to the core voltage level. It helps improve the signal by performing some kind of signal conditioning. ESD diodes associated with the input buffer help protect Integrated circuit (IC) chips from damage due to ESD events. VCC VSS PAD To Internal circuitry Output Buffer The output buffer passes data from the core to the external world which is usually another component on the Printed Circuit Board (PCB) through a track.

5 It performs level conversion from the core level voltage to the IO level output voltage (the motherboard voltage level). Output Buffers can be either 2-state or 3-state depending on the application. For a 3-state buffer, the three states are logic low, logic high and high impedance. A 3-state buffer will have an enable signal which facilitates achieving high impedance (Hi-Z) at the PAD ESD diodes associated with the output buffer also help protect ICs from damage due to ESD events. VCC VSS PAD From Internal circuitry From Internal circuitry Bi-directional Buffer A bi-directional buffer functions as both an input and an output buffer.

6 The enable signal which comes from the core determines if the buffer needs to be configured as an input buffer or an output buffer. It is designed such that when enabled as an input buffer, the PAD is at a high impedance state. There can be designs where both an input and an output buffer have separate enable signals. PAD From Internal circuitry From Internal circuitry VCC VSS To Internal circuitry Buffered Vs Unbuffered Buffered Vs Unbuffered Characteristics Buffered Unbuffered Propagation Delay High Low Noise Immunity/Margin Excellent Good Output Impedance Constant Variable Output transition time Constant Variable Output oscillation for slow inputs Yes No Input Capacitance Low High Basics of RC circuits Low Pass RC Circuit.

7 Square Wave Input If T >>RC If T = RC If T << RC RC Charging Table Low Pass RC Time Constant RC Value % of maximum Voltage Current time constant = time constant = time constant 1T = 1RC time constants = time constants = 90% time constants = time constants = time constants = If Period = 10RC If Period = 16RC If Period = 4RC Output Buffer/Driver/Transmitter Design Progressive Sizing Pre Driver requirement We cannot use a big inverter to drive a large output capacitance because, who will drive the big inverter The signal that has to drive the output cap will now see a larger gate capacitance of the BIG inverter.

8 So this results in slow rise or fall times . A unit inverter can drive approximately an inverter that's 4 times bigger in size. So say we need to drive a cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64 so that each inverter sees a same ratio of output to input cap. This is the prime reason behind going for progressive sizing. Drive Strength Calculations Let us say , with 1 Gbps to drive 5pF load Assume that a minimum of 25ohm drive strength is required So, (** R , Idrive , R 1/width of the transistor 1/Idrive ) = /2 = = 24mA Let us say per micron width of a pmos transistor Idrive = 48uA, and per micron width of a nmos transistor Idrive = 24uA, total of 500u is required in pull up and 250u required in pull down to achieve 25ohm drive strength.

9 According to GDR(Geometric Design Rules), a transistor should not exceed a 10u(assume) width in a particular technology. So we have to connect such type of transistors in parallel as many needed accordingly, in order to get the specified drive strength. Typical Driver Design VCC VSS PAD From Internal circuitry From Internal circuitry 500u 250u Typically length would depend on the technology node It is better to have maximum length such that it should have less leakage. Now -> tri-state control?

10 -> PVT control ? -> Design of diff. types of drive strengths? -> drive strength calculated at Vcc/2, why? - Due to dynamic variations of MOS transistor ON resistance Signal Integrity Analysis Transmission Lines Signal Integrity Definitions How the electrical properties of the interconnects could distort the beautiful, pristine signals from the chips Purpose of an interconnect: to transport a signal from one point to another with an acceptable level of distortion Signal integrity problems occur when the interconnects are no longer electrically transparent.