ispMACH 4000V/B/C/Z Family Data Sheet - Lattice Semi

1 4000V/B/C/Z In-System ProgrammableSuperFAST High Density PLDsMay 2009 data Sheet DS1020 TM 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brandor product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without High Performance fMAX = 400 MHz maximum operating frequency tPD = propagation delay Up to four global clock pins with programmable clock polarity control Up to 80 PTs per output Ease of Design Enhanced macrocells with individual clock, reset, preset and clock enable controls Up to four global OE controls Individual local OE control per I/O pin Excellent First-Time-FitTM and refit Fast path, SpeedLockingTM Path, and wide-PT path Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders Zero Power ( ispMACH 4000Z) and Low Power ( ispMACH 4000v /B/C) Typical static current 10 A (4032Z) Typical static current (4000C)

2 Core low dynamic power ispMACH 4000Z operational down to VCC Broad Device Offering Multiple temperature range support Commercial: 0 to 90 C junction (Tj) Industrial: -40 to 105 C junction (Tj) Extended: -40 to 130 C junction (Tj) For AEC-Q100 compliant devices, refer to LA- ispMACH 4000v /Z Automotive data Sheet Easy System Integration Superior solution for power sensitive consumer applications Operation with , or LVCMOS I/O Operation with ( 4000v ), (4000B) or (4000C/Z) supplies 5V tolerant I/O for LVCMOS , LVTTL, and PCI interfaces Hot-socketing Open-drain capability Input pull-up, pull-down or bus-keeper Programmable output slew rate PCI compatible IEEE boundary scan testable In-System Programmable (ISP ) using IEEE 1532 compliant interface I/O pins with fast setup path Lead-free package optionsTable 1.

3 ispMACH 4000v /B/C Family Selection GuideispMACH4032V/B/CispMACH4064V/B/Cisp MACH4128V/B/CispMACH4256V/B/CispMACH4384 V/B/CispMACH4512V/B/CMacrocells326412825 6384512I/O + Dedicated Inputs30+2/32+430+2/32+4/64+1064+10/92+4 /96+464+10/96+14/128+4/160+4128+4/192+41 28+4/208+4tPD (ns) (ns) (ns) (MHz)400400333322322322 Supply Voltages (V) TQFP48 TQFP44 TQFP48 TQFP100 TQFP100 TQFP128 TQFP144 TQFP1100 TQFP144 TQFP1176 TQFP256 ftBGA2/fpBGA2, 3176 TQFP256 ftBGA/fpBGA3176 TQFP256 ftBGA/fpBGA31. ( 4000v ) 128-I/O and 160-I/O Use 256 ftBGA package for all new designs. Refer to PCN#14A-07 for 256 fpBGA package SemiconductorispMACH 4000V/B/C/Z Family data Sheet2 Table 2. ispMACH 4000Z Family Selection Guide ispMACH 4000 IntroductionThe high performance ispMACH 4000 Family from Lattice offers a SuperFAST CPLD solution.

4 The Family is a blendof Lattice s two most popular architectures: the ispLSI 2000 and ispMACH 4A. Retaining the best of both families,the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with lowpower in a flexible CPLD Family . The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With itsrobust Global Routing Pool and Output Routing Pool, this Family delivers excellent First-Time-Fit, timing predictabil-ity, routing, pin-out retention and density ispMACH 4000 Family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packagesranging from 44 to 256 pins/balls.

5 Table 1 shows the macrocell, package and I/O options, along with other ispMACH 4000 Family has enhanced system integration capabilities. It supports ( 4000v ), (4000B)and (4000C/Z) supply voltages and , and interface voltages. Additionally, inputs can be safelydriven up to when an I/O bank is configured for operation, making this Family 5V tolerant. The ispMACH4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-upresistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 Family members are in-system programmable through the IEEE Standard 1532 interface. IEEE Standard boundaryscan testing capability also allows product testing on automated test equipment.

6 The 1532 interface signals TCK,TMS, TDI and TDO are referenced to VCC (logic core).OverviewThe ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnectedby a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), whichcontain multiple I/O cells. This architecture is shown in Figure 4032 ZCispMACH 4064 ZCispMACH 4128 ZCispMACH 4256 ZCMacrocells3264128256I/O + Dedicated Inputs32+4/32+432+4/32+12/64+10/64+1064+ 10/96+464+10/96+6/128+4tPD (ns) (ns) (ns) (MHz)267250220200 Supply Voltage (V) Standby Icc ( A)20253555 Pins/Package48 TQFP56 csBGA48 TQFP56 csBGA100 TQFP132 csBGA100 TQFP132csBGA100 TQFP132 csBGA176 TQFPL attice SemiconductorispMACH 4000V/B/C/Z Family data Sheet3 Figure 1. Functional Block DiagramThe I/Os in the ispMACH 4000 are split into two banks.

7 Each bank has a separate I/O power supply. Inputs cansupport a variety of standards independent of the chip or bank power supply. Outputs support the standards com-patible with the power supply provided to the bank. Support for a variety of standards helps designers implementdesigns in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is con-nected to VCCO of to for LVCMOS , LVTTL and PCI 4000 ArchitectureThere are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to beconnected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they stillmust go through the GRP.

8 This mechanism ensures that GLBs communicate with each other with consistent andpredictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associ-ated I/O cells in the I/O Logic BlockThe ispMACH 4000 GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clockgenerator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou-pled from macrocells through the ORP. Figure 2 illustrates the Bank 0I/O Bank 1I/OBlock3636 CLK0/ICLK1/ICLK2/ICLK3/I1616 Global Routing PoolVCCO0 GNDVCCO1 GND161616 Lattice SemiconductorispMACH 4000V/B/C/Z Family data Sheet4 Figure 2. Generic Logic BlockAND ArrayThe programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP areused to form 72 lines in the AND Array (true and complement of the inputs).

9 Each line in the array can be con-nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logicallocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization andShared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before beingfed to the set of five product terms from the 80 logic product terms forms a product term cluster starting with is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the Allocator36 Inputsfrom GRP16 MacrocellsTo ORPTo GRPToProduct TermOutput EnableSharing1+OE16 MC Feedback SignalsClockGenerator1+OE1+OE1+OE1+OE1+O E1+OECLK0 CLK1 CLK2 CLK31+OEAND Array36 Inputs, 83 Product TermsLattice SemiconductorispMACH 4000V/B/C/Z Family data Sheet5 Figure 3.

10 AND ArrayEnhanced Logic AllocatorWithin the logic allocator, product terms are allocated to macrocells in product term clusters. Each product termcluster is associated with a macrocell. The cluster size for the ispMACH 4000 Family is 4+1 (total 5) product software automatically considers the availability and distribution of product term clusters as it fits the functionswithin a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT SpeedLocking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability forincreased performance. The enhanced Logic Allocator of the ispMACH 4000 Family consists of the following blocks: Product Term Allocator Cluster Allocator Wide Steering LogicFigure 4 shows a macrocell slice of the Logic Allocator.