JEDEC STANDARD - Softnology

1 JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONSEPTEMBER 2012 JEDECSTANDARDDDR4 SDRAMJESD79-4 NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the STANDARD is to be used either domestically or standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes.

2 By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC STANDARD or publication may be further processed and ultimately become an ANSI claims to be in conformance with this STANDARD may be made unless all requirements stated in the STANDARD are , comments, and suggestions relative to the content of this JEDEC STANDARD or publication should be addressed to JEDEC at the address below, or refer to under standards and Documents for alternative contact information.

3 Published by JEDEC Solid State Technology Association 20123103 North 10th StreetSuite 240 SouthArlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains thecopyright on this material. By downloading this file the individual agrees not tocharge for or resell the resulting : Contact JEDECP rinted in the All rights reservedPLEASE!DON'T VIOLATETHELAW!This document is copyrighted by JEDECand may not bereproduced without information, contact: JEDEC Solid State Technology Association3103 North 10th Street, Suite 240 SouthArlington, Virginia 22201-2107or call (703) 907-7559 JEDEC STANDARD No.

4 79-4 1. Scope .. 12. DDR4 sdram Package Pinout and Addressing .. DDR4 sdram Row for X4,X8 and X16 .. DDR4 sdram Ball Pitch .. DDR4 sdram Columns for X4,X8 and X16 .. DDR4 sdram X4/8 Ballout using MO-207 .. DDR4 sdram X16 Ballout using MO-207 .. Pinout Description .. DDR4 sdram Addressing ..73. Functional Description .. Simplified State Diagram .. Basic RESET and Initialization Procedure .. Power-up Initialization Sequence .. Reset Initialization with Stable Power .. Register Definition.

5 Programming the mode registers .. Mode Register ..134. DDR4 sdram Command Description and Operation .. Command Truth Table .. CKE Truth Table .. Burst Length, Type and Order .. BL8 Burst order with CRC Enabled .. DLL-off Mode & DLL on/off Switching procedure .. DLL on/off switching procedure .. DLL on to DLL off Procedure .. DLL off to DLL on Procedure .. DLL-off Mode .. Input Clock Frequency Change .. Write Leveling .. DRAM setting for write leveling & DRAM termination function in that mode.

6 Procedure Description .. Write Leveling Mode Exit .. Temperature controlled Refresh modes .. Normal temperature mode .. Extended temperature mode .. Fine Granularity Refresh Mode .. Mode Register and Command Truth Table .. tREFI and tRFC parameters .. Changing Refresh Rate .. Usage with Temperature Controlled Refresh Self Refresh entry and exit .. Multi Purpose Register .. DQ Training with MPR .. MR3 definition .. MPR MPR Writes .. MPR Read Data format .. Data Mask(DM), Data Bus Inversion (DBI) and ZQ Calibration Commands.

7 50 DDR4 sdram STANDARD (From JEDEC Board Ballot JCB-12-40, formulated under the cognizance of the Subcommittee on -i-DRAM Memories.)ContentsJEDEC STANDARD No. ZQ Calibration Description .. DQ Vref Training .. Per DRAM Addressability .. CAL Mode (CS_n to Command Address Latency) .. CAL Mode Description .. CRC .. CRC Polynomial and logic equation .. CRC data bit mapping for x8 devices .. CRC data bit mapping for x4 devices .. CRC data bit mapping for x16 devices .. Write CRC for x4, x8 and x16 devices.

8 CRC Error Handling .. CRC Frame format with BC4 .. Simultaneous DM and CRC Functionality .. Command Address Parity( CA Parity ) .. CA Parity Error Log Readout .. Control Gear Down Mode .. DDR4 Key Core Programmable Preamble .. Write Preamble .. Read Preamble .. Read Preamble Training .. Postamble .. Read Write Postamble .. ACTIVATE Command .. Precharge Command .. Read READ Timing Definitions .. READ Timing; Clock to Data Strobe relationship .. READ Timing; Data Strobe to Data relationship.

9 TLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation .. tRPRE Calculation .. tRPST Calculation .. READ Burst Operation .. Burst Read Operation followed by a Precharge .. Burst Read Operation with Read DBI (Data Bus Inversion) .. Burst Read Operation with Command/Address Parity .. Read to Write with Write CRC .. Read to Read with CS to CA Latency .. Write Operation .. Write Burst Operation .. Refresh Command .. Self refresh Operation .. Low Power Auto Self Refresh .. Power down Mode.

10 Power-Down Entry and Exit .. Power-Down clarifications .. Maximum Power Saving Mode .. Maximum power saving Mode entry .. CKE transition during the mode .. Mode exit .. Timing parameter bin of Maximum Power Saving Mode for DDR4-1600/1866/2133/2400/2666/3200 Connectivity Test Mode .. Introduction .. Pin Mapping .. Logic Equations .. Min Term Equations .. 136-ii- JEDEC STANDARD No. 79-4 Output equations for x16 devices .. Output equations for x8 devices .. Output equations for x4 devices.