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1 24 ~The first step is the only difficulty. I Content 0 .. 1 1 FPGA .. 2 2 FPGA .. 3 FPGA .. 4 .. 4 .. 5 .. 6 .. 6 .. 8 .. 8 .. 8 .. 9 .. 9 .. 10 IC .. 10 .. 11 7 LED .. 11 USB .. 12 FPGA .. 13 FPGA .. 13 .. 14 3 FPGA .. 15 ISE(Integrated Software Environment) .. 15 .. 15 VerilogHDL .. 15 VHDL .. 15 4 VerilogHDL .. 16 VerilogHDL .. 16 .. 16 .. 19 .. 22 .. 38 5.

2 40 .. 40 .. 40 .. 41 .. 47 .. 49 6 .. 57 .. 57 7 .. 63 .. 63 8 Appendix .. 64 VerilogHDL .. 64 TOP Module .. 64 U0 Module .. 71 U1 Module .. 72 II U2 Module .. 74 U3 Module .. 75 U4 Module .. 77 U5 Module .. 78 U6 Module .. 80 .. 82 1 VerilogHDL FPGA FPGA FPGA ISE webPACK VerilogHDL FPGA

3 FPGA FPGA FPGA FPGA FPGA FPGA FPGA ISE HDL HDL VerilogHDL VerilogHDL 0 2 1 FPGA OS FPGA 3 2 FPGA FPGA Field Programmable Gate Array FPGA IP FPGA PLD PAL AND-OR FPGA LUT look-up table LUT LUT

4 FPGA 4 FPGA FPGA FPGA FPGA FPGA Xilinx XC3S100E-4 VQG100C 7 LED USB PC JTAG FPGA COM USB FPGA DC USB DC 6V 12V AC FPGA RS-232C Dsub9 RS-232C FPGA FPGA Parallax FPGA FPGA CAN(Control Area Network) CAN CAN MCP2515 CAN FPGA LED 8 FPGA SW 8 FPGA XC3S100E 5 x 4 100uF25V 25PK100 MEFC5X11 22 RPEF11H104Z2P1 1 33 1/4W RD-25TJ330 1 120 1/4W RD-25TJ121 17 330 1/4W RD-25TJ331 19 1K 1/4W RD-25TJ102 4 10K 1/4W RD25S 10K 1 FPGA IEEC-DI001A 1 1 10 MHz CSTLS10M0G53-B0 4 2SA1015Y 1 5V NJU7223F50 1 NJU7223F33 1 RS232C ICL3232 CPZ 1 CAN MCP2515-I/P 9 LED OSDR3133A 1 4

5 7 LED OSL40562-IG 7 P-03688 6 P-00298 1 MJ-179P 1 2P B2B-XH 1 Dsub9 C-00644 3 3P B3B-XH 8 DTS-6 2 10mmM3 2 M3 1 USB C-05222 1 M-05400 3 C-05779 3 C-00167 1 USB M-02990 1 AVES-XC3S1 E 6 x 20 1 19 2 8 1 7 1 3 4 2 1 20 1 19 2 8 1 7 1 3 1 2 1 x x IC 20 19 8 7 3 2 20 19 8 7 3 2 7 x FPGA 8 R1 R42 R5 R26 C1 C4 x 9 SW1 SW8 Q1 Q4 x 10 D1 D9 x x IC JP1 4 X2 X1 U8 U9 IC IC

6 IC 11 IC J1 J7 J2 J5 J7 7 LED D10 7 LED x 7 LED DP DP 7 LED 12 7 LED USB U3 USB USB U1 U2 USB 13 FPGA FPGA x FPGA FPGA FPGA FPGA FPGA FPGA FPGA 3 3 20 8 7 2 19 19 20 8 7 2 19 19 14 Dsub J4 FPGA FPGA 3 USB IO 2 USB ON/OFF FPAG USB DC USB DC USB COM Dsub9 RS-232C Dsub9 RS-232C USB COM CAN ON/OFF CAN CAN CAN / JACK USB JP1 TX JP3 RX JP2 TX JP3 RX JP2 JACK USB JP1

7 15 3 FPGA ISE(Integrated Software Environment) ISE Xilinx PLD HDL HDL JTAG Xilinx ISE ISE WebPACK Xilinx VerilogHDL 1364-2005 VHDL Electronic Design Automation 1076-2008 16 4 VerilogHDL VerilogHDL VerilogHDL module ; input ; output ; wire ; reg ; assign ; always @( ) begin ff_q <= x.

8 End endmodule 17 NOT 18 VerilogHDL module

9 Majority(IN_A, IN_B, IN_C, OUT_X); input IN_A, IN_B, IN_C; output OUT_X; wire AND_BC, AND_AC, AND_AB; assign AND_BC = IN_B assign AND_AC = IN_A assign AND_AB = IN_A X assign OUT_X = AND_BC | AND_AC | AND_AB; endmodule NET # INPUT PIN NET "IN_A" LOC = "P35"; # SW1 NET "IN_B" LOC = "P34"; # SW2 NET "IN_C" LOC = "P33"; # SW3 # OUTPUT PIN NET "OUT_X" LOC = "P54"; # LED1 19