Lecture 11: RISC-V - University of California, Berkeley

1 EE141 EECS 151/251A Spring 2020 Digital Design and Integrated CircuitsInstructor: John WawrzynekLecture 11: RISC-VEE141 Project Introduction You will design and optimize a RISC-V processor Phase 1: Design and demonstrate a processor Phase 2: ASIC Lab implement cache memory and generate complete chip layout FPGA Lab Add video display and graphics accelerator 2 Today discuss how to design the processorWhat is RISC-V ? Fifth generation of RISC design from UC Berkeley A high-quality, license-free, royalty-free RISC ISA specification Experiencing rapid uptake in both industry and academia Supported by growing shared software ecosystem Appropriate for all levels of computing system, from micro-controllers to supercomputers 32-bit, 64-bit, and 128-bit variants (we re using 32-bit in class, textbook uses 64-bit) Standard maintained by non-profit RISC-V Foundation 3 Members (60+) 4 Rumble DevelopmentPlatinum:Gold, Silver, Auditors: instruction set Architecture (ISA) Job of a CPU (Central Processing Unit, aka Core): execute instructions instructions : CPU s primitives operations instructions performed one after another in sequence Each instruction does a small amount of work (a tiny part of a larger program).

2 Each instruction has an operation applied to operands, and might be used change the sequence of instruction. CPUs belong to families, each implementing its own set of instructions CPU s particular set of instructions implements an instruction set Architecture (ISA) Examples: ARM, Intel x86, MIPS, RISC-V , IBM/Motorola PowerPC (old Mac), Intel IA64, .. 5If you need more info on processor Processor instructions in Brief Compilers generate machine instructions to execute your programs in the following way: Load/Store instructions move operands between main memory (cache hierarchy) and core register file. Register/Register instructions perform arithmetic and logical operations on register file values as operands and result returned to register file. Register/Immediate instructions perform arithmetic and logical operations on register file value and constants. Branch instructions are used for looping and if-than-else (data dependent operations).

3 Jumps are used for function call and return. 6 IMEM+4rs2rs1rdReg[]ALUDMEMimmPCmuxComple te RV32I ISA 7 Not in EECS151/251A** implemented in the ASIC projectComputer Science 61C Spring 2018 Wawrzynek and WeaverSummary of RISC-V Instruction Formats 8 Binary encoding of machine instructions . Note the common fields. State Required by RV32I ISAEach instruction reads and updates this state during execution: Registers ( ) Register file (or regfile) Reg holds 32 registers x 32 bits/register: Reg[0].. Reg[31] First register read specified by rs1 field in instruction Second register read specified by rs2 field in instruction Write register (destination) specified by rd field in instruction x0 is always 0 (writes to Reg[0]are ignored) Program Counter (PC) Holds address of current instruction Memory (MEM) Holds both instructions & data, in one 32-bit byte-addressed memory space We ll use separate memories for instructions (IMEM) and data (DMEM) Later we ll replace these with instruction and data caches instructions are read (fetched) from instruction memory (assume IMEM read-only) Load/store instructions access data memory 9EE141 RISC-V State Elements 10 State encodes everything about the execution status of a processor: PC register 32 registers MemoryNote: for these state elements, clock is used for write but not for read (asynchronous read, synchronous write).

4 EE141 EECS150 - Lec07-MIPSRISC-V Microarchitecture Oganization 11 Datapath + Controller + External MemoryControllerEE141 MicroarchitectureMultiple implementations for a single instruction set architecture: Single-cycle Each instruction executes in a single clock cycle. Multicycle Each instruction is broken up into a series of shorter steps with one step per clock cycle. Pipelined (variant on multicycle ) Each instruction is broken up into a series of steps with one step per clock cycle Multiple instructions execute at once by overlapping in time. Superscalar Multiple functional units to execute multiple instructions at the same time Out of instructions are reordered by the hardware 12 First Design: One-Instruction-Per-Cycle RISC-V state outputs drive the inputs to the combinational logic, whose outputs settles at the values of the state before the next clock edge the rising clock edge, all the state elements are updated with the combinational logic outputs, and execution moves to the next clock cycle (next instruction) 13 Reg[]pcIMEMDMEMC ombinational LogicclockOn every tick of the clock, the computer executes one instructionBasic Phases of Instruction Execution1.

5 Instruction Fetch2. Decode/ Register Read3. Execute4. Memory5. Register Write 14 IMEM+4rs2rs1rdReg[]ALUDMEMimmPCmuxClockt imeImplementing the add instructionadd rd, rs1, rs2 Instruction makes two changes to machine s state: Reg[rd] = Reg[rs1] + Reg[rs2] PC = PC + 4 15 Control LogicDatapath for add 16+4pcpc+4inst[11:7]inst[19:15]inst[24:2 0]IMEM inst[31:0]Reg[]AddrAAddrBDataAAddrDDataB DataDReg[rs1]Reg[rs2]+alu(RegWriteEnable )RegWEn (1=write, 0=no write)Timing Diagram for add 1710001004PC10041008PC+4add x1,x2,x3add x6,x7,x9inst[31:0]Clocktime+4pcpc+4inst[ 11:7]inst[19:15]inst[24:20]IMEM inst[31:0]+RegWEnReg[]AddrAAddrBDataAAdd rDDataBDataDReg[rs1]Reg[rs2]clockaluReg[ 2]Reg[7]Reg[rs1]Reg[2]+Reg[3]aluReg[7]+R eg[9]Reg[3]Reg[9]Reg[rs2]???Reg[1]Reg[2] +Reg[3]Implementing the sub instructionsub rd, rs1, rs2 Reg[rd] = Reg[rs1] - Reg[rs2] Almost the same as add, except now have to subtract operands instead of adding them inst[30] selects between add and subtract 18 Control LogicDatapath for add/sub 19+4pcpc+4inst[11:7]inst[19:15]inst[24:2 0]IMEM inst[31:0]RegWEn (1=write, 0=no write)Reg[]AddrAAddrBDataAAddrDDataBData DReg[rs1]Reg[rs2]aluALUALUSel (Add=0/Sub=1)Implementing other R-Format instructions All implemented by decoding funct3 and funct7 fields and selecting appropriate ALU function 20 Implementing the addi instruction RISC-V Assembly Instruction: addi rd, rs1, integer Reg[rd] = Reg[rs1] + sign_extend(immediate) example: addi x15,x1,-50 2111111100111000001000011110010011OP-Imm rd=15 ADDimm=-50rs1=1 Uses the I-type instruction formatControl LogicReview: Datapath for add/sub 22+4pcpc+4inst[11:7]inst[19:15]inst[24:2 0]IMEM inst[31.]

6 0]RegWEn (1=write, 0=no write)Reg[]AddrAAddrBDataAAddrDDataBData DReg[rs1]Reg[rs2]aluALUALUSel (Add=0/Sub=1)Control LogicAdding addi to datapath 23+4pcpc+4inst[11:7]inst[19:15]inst[24:2 0]IMEM inst[31:0]Reg[]AddrAAddrBDataAAddrDDataB DataDReg[rs1]Reg[rs2]aluALUALUSel=AddImm . Gen01 RegWEn=1inst[31:20]imm[31:0]ImmSel=IBSel =1I-type Format immediates 24inst[31:0]------inst[31]-(sign-extensi on)-------inst[30:20]imm[31:0]Imm. Geninst[31:20]imm[31:0]ImmSel=I High 12 bits of instruction (inst[31:20]) copied to low 12 bits of immediate (imm[11:0]) Immediate is sign-extended by copying value of inst[31] to fill the upper 20 bits of the immediate value (imm[31:12])Control LogicAdding addi to datapathCS 61c 25+4pcpc+4inst[11:7]inst[19:15]inst[24:2 0]IMEM inst[31:0]Reg[]AddrAAddrBDataAAddrDDataB DataDReg[rs1]Reg[rs2]aluALUALUSel=AddImm . Gen01 RegWEn=1inst[31:20]imm[31:0]ImmSel=IBSel =1 Also works for all other I-format arithmetic instruction (slti,sltiu,andi,ori,xori,slli,srli,srai ) just by changing ALUSelImplementing Load Word instruction RISC-V Assembly Instruction: lw rd, integer(rs1) Reg[rd] = DMEM[Reg[rs1] + sign_extend(immediate)] example: addi x14,8(x2) 2600000000100000010010011100000011 LOADrd=14 LWimm=+8rs1=2 Also uses the I-type instruction formatControl LogicReview: Adding addi to datapath 27+4pcpc+4inst[11:7]inst[19:15]inst[24:2 0]IMEM inst[31:0]Reg[]AddrAAddrBDataAAddrDDataB DataDReg[rs1]Reg[rs2]aluALUALUSel=AddImm .

7 Gen01 RegWEn=1inst[31:20]imm[31:0]ImmSel=IBSel =1 Adding lw to datapath 28 IMEMALUImm. Gen+4 DMEMReg[]AddrAAddrBDataAAddrDDataBDataDA ddrDataR01pc01inst[11:7]inst[19:15]inst[ 24:20]inst[31:20]alumemwbpc+4 Reg[rs1]imm[31:0]Reg[rs2]inst[31:0]ImmSe lRegWEnBSelALUSelMemRWWBS elwbAdding lw to datapathCS 61c 29 IMEMALUImm. Gen+4 DMEMReg[]AddrAAddrBDataAAddrDDataBDataDA ddrDataR01pc01inst[11:7]inst[19:15]inst[ 24:20]inst[31:20]alumemwbpc+4 Reg[rs1]imm[31:0]Reg[rs2]inst[31:0]ImmSe l=IRegWEn=1 BSel=1 ALUSel=addMemRW=ReadWBSel=0wbAll RV32 Load instructions Supporting the narrower loads requires additional circuits to extract the correct byte/halfword from the value loaded from memory, and sign- or zero-extend the result to 32 bits before writing back to register file. 30funct3 field encodes size and signedness of load dataImplementing Store Word instruction RISC-V Assembly Instruction: sw rs2, integer(rs1) DMEM[Reg[rs1] + sign_extend(immediate)] = Reg[rs2] example: sw x14, 8(x2) 3100000000111000010010010000100011 STORE offset[4:0] =8 SWoffset[11:5] =0rs2=14rs1=2combined 12-bit offset = 8000000001000 Uses the S-type instruction formatReview: Adding lw to datapath 32 IMEMALUImm.

8 Gen+4 DMEMReg[]AddrAAddrBDataAAddrDDataBDataDA ddrDataR01pc01inst[11:7]inst[19:15]inst[ 24:20]inst[31:20]alumemwbpc+4 Reg[rs1]imm[31:0]Reg[rs2]inst[31:0]ImmSe lRegWEnBSelALUSelMemRWWBS elwbAdding sw to datapath 33 IMEMALUImm. Gen+4 DMEMReg[]AddrAAddrBDataAAddrDDataBDataDA ddrDataWDataR01pc01inst[11:7]inst[19:15] inst[24:20]inst[31:7]alumemwbpc+4 Reg[rs1]imm[31:0]Reg[rs2]inst[31:0]ImmSe l=SRegWEn=0 Bsel=1 ALUSel=AddMemRW=WriteWBSel=*wb*= Don t Care CS 61c 34 IMEMALUImm. Gen+4 DMEMReg[]AddrAAddrBDataAAddrDDataBDataDA ddrDataR01pc01inst[11:7]inst[19:15]inst[ 24:20]inst[31:7]alumemwbpc+4 Reg[rs1]imm[31:0]Reg[rs2]inst[31:0]ImmSe l=SRegWEnBSel=1 ALUSel=AddMemRW=WriteWBSel=*wbAdding sw to datapath*= Don t Care Review: I-Format immediates 35inst[31:0]------inst[31]-(sign-extensi on)-------inst[30:20]imm[31:0]Imm. Geninst[31:20]imm[31:0]ImmSel=I High 12 bits of instruction (inst[31:20]) copied to low 12 bits of immediate (imm[11:0]) Immediate is sign-extended by copying value of inst[31] to fill the upper 20 bits of the immediate value (imm[31:12])I & S -type Immediate Generator 36imm[11:5]rs2rs1funct3imm[4:0]S-opcodei mm[11:0]rs1funct3rdI-opcodeinst[31](sign -extension)inst[30:25]imm[31:0]inst[31:0 ]inst[24:20]SIinst[31](sign-extension)in st[30:25]inst[11.]

9 7]0671112141519202425310451011311655SI Just need a 5-bit mux to select between two positions where low five bits of immediate can reside in instruction Other bits in immediate are wired to fixed positions in instructionImplementing Branches B-format is mostly same as S-Format, with two register sources (rs1/rs2) and a 12-bit immediate But now immediate represents values -4096 to +4094 in 2-byte increments The 12 immediate bits encode even 13-bit signed byte offsets (lowest bit of offset is always zero, so no need to store it) 37 Uses the B-type instruction format RISC-V Assembly Instruction, example: beq rs1, rs2, label if rs1==rs2 pc pc + offset // offset computed by compiler/assembler and stored in the immediate field(s) example: beq x1, x2, L1 Review: Adding sw to datapath 38 IMEMALUImm. Gen+4 DMEMReg[]AddrAAddrBDataAAddrDDataBDataDA ddrDataWDataR01pc01inst[11:7]inst[19:15] inst[24:20]inst[31:7]alumemwbpc+4 Reg[rs1]imm[31:0]Reg[rs2]inst[31:0]ImmSe lRegWEnBselALUSelMemRWWBSel=wbAdding branches to datapath 39 IMEMALUImm.

10 Gen+4 DMEMB ranch []AddrAAddrBDataAAddrDDataBDataDAddrData WDataR100110pc01inst[11:7]inst[19:15]ins t[24:20]inst[31:7]alumemwbalupc+4 Reg[rs1]pcimm[31:0]Reg[rs2]inst[31:0]Imm SelRegWEnBrUnBrEqBrLTASelBSelALUSelMemRW WBSelPCSelwbAdding branches to datapath 40 IMEMALUImm. Gen+4 DMEMB ranch []AddrAAddrBDataAAddrDDataBDataDAddrData WDataR100110pc01inst[11:7]inst[19:15]ins t[24:20]inst[31:7]alumemwbalupc+4pcimm[3 1:0]Reg[rs2]wbinst[31:0]ImmSel=BRegWEn=0 BrUnBrEqBrLTASel=1 Bsel=1 ALUSel=AddMemRW=ReadWBSel=*PCSel=taken/n ot-takenReg[rs1]Branch Comparator BrEq = 1, if A=B BrLT = 1, if A < B BrUn =1 selects unsigned comparison for BrLT, 0=signed BGE branch: A >= B, if !(A<B) 41 Branch Branch Immediates 12-bit immediate encodes PC-relative offset of -4096 to +4094 bytes in multiples of 2 bytes RISC-V approach: keep 11 immediate bits in fixed position in output value, and rotate LSB of S-format to be bit 12 of B-format 42sign=imm[11]imm[10:5]imm[4:0]sign=imm[ 12]imm[10:5]imm[4:1]0S-ImmediateB-Immedi ate (shift left by 1)Only one bit changes position between S and B, so only need a single-bit 2-way muximm[11] RISC-V Immediate Encoding 43 Instruction Encodings, inst[31:0]32-bit immediates produced, imm[31:0]Only bit 7 of instruction changes role in immediate between S and BUpper bits sign-extended from inst[31] alwaysImplementing JALR Instruction (I-Format) JALR rd, rs, immediate Writes PC+4 to Reg[rd] (return address) Sets PC = Reg[rs1] + offset Uses same immediates as arithmetic and loads no multiplication by 2 bytes 44 Review.