LM5050-1, LM5050-1-Q1 High-Side OR-ing FET Controller ...

1 Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design LM5050-1, LM5050-1-Q1 . SNVS629F MAY 2011 REVISED DECEMBER 2019. LM5050-1, LM5050-1-Q1 High-Side OR-ing FET Controller 1 Features 3 Description 1 Available in Standard and AEC-Q100 Qualified The LM5050-1/-Q1 High Side OR-ing FET Controller Versions LM5050Q0MK-1 (up to 150 C TJ) and operates in conjunction with an external MOSFET as an ideal diode rectifier when connected in series with LM5050Q1MK-1 (up to 125 C TJ). a power source. This ORing Controller allows Functional safety capable MOSFETs to replace diode rectifiers in power Documentation available to aid functional distribution networks thus reducing both power loss safety system design and voltage drops. Wide Operating Input Voltage Range, VIN: 1 V to The LM5050-1/-Q1 Controller provides charge pump 75 V (VBIAS required for VIN < 5 V) gate drive for an external N-Channel MOSFET and a 100-V Transient Capability fast response comparator to turn off the FET when current flows in the reverse direction.

2 The LM5050-1/- Charge Pump Gate Driver for External N-Channel Q1 can connect power supplies ranging from 5 V to MOSFET 75 V and can withstand transients up to 100 V. Fast 50-ns Response to Current Reversal 2-A Peak Gate Turnoff Current Device Information(1). Minimum VDS Clamp for Faster Turnoff PART NUMBER PACKAGE BODY SIZE (NOM). LM5050-1. Package: SOT-6 (Thin SOT-23-6) SOT (6) mm mm LM5050-1-Q1 . 2 Applications (1) For all available packages, see the orderable addendum at the end of the data sheet. Active OR-ing of Redundant (N+1) Power Supplies Full Application VIN VOUT. + to +75V. 100: IN GATE OUT. VS. LM5050-1. Low= FET On, High= FET Off Shutdown OFF. GND PF. GND GND. Typical Redundant Supply Configuration PS1 IN GATE OUT. LM5050-1 VS. GND. CLOAD RLOAD. PS2 IN GATE OUT. LM5050-1 VS. GND. 1. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers.

3 PRODUCTION DATA. LM5050-1, LM5050-1-Q1 . SNVS629F MAY 2011 REVISED DECEMBER 2019 Table of Contents 1 Features .. 1 Device Functional 13. 2 Applications .. 1 8 Application and Implementation .. 14. 3 Description .. 1 Application 14. 4 Revision 2 Typical Applications .. 16. 5 Pin Configuration and Functions .. 3 9 Power Supply 21. 6 4 10 21. Absolute Maximum Ratings .. 4 Layout Guidelines .. 21. ESD Ratings: LM5050-1 .. 4 Layout Example .. 21. ESD Ratings: LM5050-1-Q1 .. 4 11 Device and Documentation Support .. 22. Recommended Operating 4 Documentation Support .. 22. Thermal Information .. 4 Related Links .. 22. Electrical 5 Community 22. Typical Characteristics .. 8 Trademarks .. 22. 7 Detailed Description .. 11 Electrostatic Discharge Caution .. 22. Overview .. 11 Glossary .. 22. Functional Block Diagram .. 12 12 Mechanical, Packaging, and Orderable Feature 12 Information .. 22. 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

4 Changes from Revision E (December 2015) to Revision F Page Added Functional safety capable link to the Features section .. 1. Changes from Revision D (June 2013) to Revision E Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .. 1. 2 Submit Documentation Feedback Copyright 2011 2019, Texas Instruments Incorporated Product Folder Links: LM5050-1 LM5050-1-Q1 . LM5050-1, LM5050-1-Q1 . SNVS629F MAY 2011 REVISED DECEMBER 2019. 5 Pin Configuration and Functions DDC Package 6-Pin SOT. Top View VS 1 6 OUT. LM5050MK-1. GND 2 5 GATE. OFF 3 4 IN. Pin Functions PIN. I/O DESCRIPTION. NO. NAME. The main supply pin for all internal biasing and an auxiliary supply for the internal gate drive 1 VS I. charge pump. Typically connected to either VOUT or VIN; a separate supply can also be used.

5 2 GND PWR Ground return for the Controller A logic high state at the OFF pin will pull the GATE pin low and turn off the external MOSFET. 3 OFF I Note that when the MOSFET is off, current will still conduct through the FET's body diode. This pin should may be left open or connected to GND if unused. 4 IN I Voltage sense connection to the external MOSFET Source pin. Connect to the Gate of the external MOSFET. Controls the MOSFET to emulate a low forward- 5 GATE O. voltage diode. 6 OUT O Voltage sense connection to the external MOSFET Drain pin. Copyright 2011 2019, Texas Instruments Incorporated Submit Documentation Feedback 3. Product Folder Links: LM5050-1 LM5050-1-Q1 . LM5050-1, LM5050-1-Q1 . SNVS629F MAY 2011 REVISED DECEMBER 2019 6 Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1). MIN MAX UNIT. IN, OUT Pins to Ground (2) 100 V. (2). GATE Pin to Ground 100 V. VS Pin to Ground 100 V. OFF Pin to Ground 7 V.

6 Storage Temperature 65 150 C. (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The GATE pin voltage is typically 12 V above the IN pin voltage when the LM5050-1 is enabled (that is, OFF Pin is Open or Low, and VIN > VOUT). Therefore, the absolute maximum rating for the IN pin voltage applies only when the LM5050-1 is disabled (that is, OFF. Pin is logic high), or for a momentary surge to that voltage because the Absolute Maximum Rating for the GATE pin is also 100 V. ESD Ratings: LM5050-1. VALUE UNIT. Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000. V(ESD) Electrostatic discharge V. Machine model (MM) (2) 150.

7 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) The MM is a 200-pF capacitor discharged through a 0- resistor (that is, directly) into each pin. Applicable test standard is JESD-A115- A. ESD Ratings: LM5050-1-Q1 . VALUE UNIT. (1). Human-body model (HBM), per AEC Q100-002 2000. V(ESD) Electrostatic discharge V. Machine model (MM) (2) 150. (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. (2) The MM is a 200-pF capacitor discharged through a 0- resistor (that is, directly) into each pin. Applicable test standard is JESD-A115- A. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted). MIN MAX UNIT. IN, OUT, VS Pins 5 75 V. OFF Pin 0 V. Standard Grade 40 125 C. Junction Temperature (TJ) LM5050Q0MK-1 40 150 C. LM5050Q1MK-1 40 125 C. Thermal Information LM5050-1/-Q1. THERMAL METRIC (1) DDC (SOT) UNIT.

8 6 PINS. R JA Junction-to-ambient thermal resistance C/W. R JC(top) Junction-to-case (top) thermal resistance C/W. R JB Junction-to-board thermal resistance C/W. JT Junction-to-top characterization parameter C/W. JB Junction-to-board characterization parameter C/W. (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 4 Submit Documentation Feedback Copyright 2011 2019, Texas Instruments Incorporated Product Folder Links: LM5050-1 LM5050-1-Q1 . LM5050-1, LM5050-1-Q1 . SNVS629F MAY 2011 REVISED DECEMBER 2019. Thermal Information (continued). LM5050-1/-Q1. THERMAL METRIC (1) DDC (SOT) UNIT. 6 PINS. R JC(bot) Junction-to-case (bottom) thermal resistance N/A C/W. Electrical Characteristics Typical values represent the most likely parametric norm at TJ = 25 C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V, VVS = VIN, VOUT = VIN, VOFF = 0 V, CGATE= 47 nF, and TJ = 25 C.

9 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT. VS PIN. Operating VVS Supply Voltage TJ = 40 C to 125 C 5 75 V. Range VVS= 5 V, VIN = 5 V TJ = 25 C 75. VOUT = VIN - 100 mV TJ = 40 C to 125 C 105. Operating VVS= 12 V, VIN = 12 V TJ = 25 C 100. IVS A. Supply Current VOUT = VIN - 100 mV TJ = 40 C to 125 C 147. VVS= 75 V, VIN = 75 V TJ = 25 C 130. VOUT = VIN - 100 mV TJ = 40 C to 125 C 288. IN PIN. Operating Input VIN TJ = 40 C to 125 C 5 75 V. Voltage Range VIN = 5 V TJ = 25 C 190. VVS= VIN. VOUT = VIN - 100 mV TJ = 40 C to 125 C 32 305. GATE = Open IIN IN Pin current TJ = 25 C 320 A. VIN = 12 V to 75 V. VVS= VIN LM5050MK-1, TJ = 40 C to 125 C 233 400. VOUT = VIN - 100 mV LM5050Q1MK-1. GATE = Open TJ = 40 C to 125 C LM5050Q0MK-1 233 475. OUT PIN. Operating VOUT Output Voltage TJ = 40 C to 125 C 5 75 V. Range VIN = 5 V to 75 V TJ = 25 C IOUT OUT Pin Current VVS= VIN A. VOUT = VIN - 100 mV TJ = 40 C to 125 C 8. GATE PIN. VIN = 5 V TJ = 25 C 30. VVS = VIN. VGATE = VIN TJ = 40 C to 125 C 12 41.

10 Gate Pin Source VOUT = VIN - 175 mV. IGATE(ON) A. Current VIN = 12 V to 75 V TJ = 25 C 32. VVS = VIN. VGATE = VIN TJ = 40 C to 125 C 20 41. VOUT = VIN - 175 mV. VIN = 5 V TJ = 25 C 7. VVS = VIN. VGATE - VIN in VOUT = VIN - 175 mV TJ = 40 C to 125 C 4 9. VGS Forward V. Operation (1) VIN = 12 V to 75 V TJ = 25 C 12. VVS = VIN. VOUT = VIN - 175 mV TJ = 40 C to 125 C 9 14. (1) Measurement of VGS voltage (that is. VGATE - VIN) includes 1 M in parallel with CGATE. Copyright 2011 2019, Texas Instruments Incorporated Submit Documentation Feedback 5. Product Folder Links: LM5050-1 LM5050-1-Q1 . LM5050-1, LM5050-1-Q1 . SNVS629F MAY 2011 REVISED DECEMBER 2019 Electrical Characteristics (continued). Typical values represent the most likely parametric norm at TJ = 25 C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V, VVS = VIN, VOUT = VIN, VOFF = 0 V, CGATE= 47 nF, and TJ = 25 C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT.