LMC6482 CMOS Dual Rail-To-Rail Input and Output ...

1 Product Sample & Technical Tools & Support &. Folder Buy Documents Software Community LMC6482 . SNOS674E NOVEMBER 1997 REVISED APRIL 2015. LMC6482 CMOS Dual Rail-To-Rail Input and Output Operational Amplifier 1 Features 3 Description . 1 Typical Unless Otherwise Noted The LMC6482 device provides a common-mode range that extends to both supply rails. This Rail-To-Rail Rail-To-Rail Input Common-Mode Voltage Range performance combined with excellent accuracy, due (Ensured Over Temperature) to a high CMRR, makes it unique among Rail-To-Rail Rail-To-Rail Output Swing (Within 20-mV of Supply Input amplifiers. The device is ideal for systems, such rail , 100-k Load) as data acquisition, that require a large Input signal Ensured 3-V, 5-V, and 15-V Performance range. The LMC6482 is also an excellent upgrade for circuits using limited common-mode range amplifiers Excellent CMRR and PSRR: 82 dB such as the TLC272 and TLC277.

2 Ultralow Input Current: 20 fA. Maximum dynamic signal range is assured in low High Voltage Gain (R L = 500 k ): 130 dB voltage and single supply systems by the Rail-To-Rail Specified for 2-k and 600- Loads Output swing of the LMC6482 . The Rail-To-Rail Output Power-Good Output swing is ensured for loads down to 600 of the device. Ensured low-voltage characteristics and low- Available in VSSOP Package power dissipation make the LMC6482 especially well- suited for battery-operated systems. LMC6482 is also 2 Applications available in a VSSOP package, which is almost half Data Acquisition Systems the size of a SOIC-8 device. See the LMC6484 data sheet for a quad CMOS operational amplifier with Transducer Amplifiers these same features. Hand-held Analytic Instruments Medical Instrumentation Device Information(1). Active Filter, Peak Detector, Sample and Hold, pH PART NUMBER PACKAGE BODY SIZE (NOM).

3 Meter, Current Source SOIC (8) mm mm Improved Replacement for TLC272, TLC277 LMC6482 VSSOP (8) mm mm PDIP (8) mm mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Rail-To-Rail Input Rail-To-Rail Output A1 V A2 V. 3V 3V. 0V 0V. 500mV 50 s 500mV 50 s C001 C002. 1. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMC6482 . SNOS674E NOVEMBER 1997 REVISED APRIL 2015 Table of Contents 1 Features .. 1 Functional Block Diagram .. 18. 2 Applications .. 1 Feature 18. 3 Description .. 1 Device Functional 19. 4 Revision 2 8 Application and Implementation .. 20. Application 20. 5 Pin Configuration and Functions .. 3. Typical Applications .. 22. 6 3. Absolute Maximum Ratings.

4 3 9 Power Supply 28. ESD 4 10 28. Recommended Operating 4 Layout Guidelines .. 28. Thermal Information .. 4 Layout Example .. 28. Electrical Characteristics for V+ = 5 4 11 Device and Documentation Support .. 30. Electrical Characteristics for V+ = 3 7 Trademarks .. 30. Typical Characteristics .. 9 Electrostatic Discharge Caution .. 30. 7 Detailed Description .. 18 Glossary .. 30. Overview .. 18 12 Mechanical, Packaging, and Orderable Information .. 30. 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (March 2013) to Revision E Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.

5 1. Changes from Revision C (March 2013) to Revision D Page Changed layout of National Data Sheet to TI format .. 27. 2 Submit Documentation Feedback Copyright 1997 2015, Texas Instruments Incorporated Product Folder Links: LMC6482 . LMC6482 . SNOS674E NOVEMBER 1997 REVISED APRIL 2015. 5 Pin Configuration and Functions D, DGK and P Packages 8-Pin SOIC, VSSOP and PDIP. (Top View). Pin Functions PIN. TYPE DESCRIPTION. NO. NAME. 1 Output A O Output for Amplifier A. 2 INVERTING Input A I Inverting Input for Amplifier A. 3 NONINVERTING Input A I Noninverting Input for Amplifier A. 4 V P Negative supply voltage Input 5 NONINVERTING Input B I Noninverting Input for Amplifier B. 6 INVERTING Input B I Inverting Input for Amplifier B. 7 Output B O Output for Amplifier B. 8 V+ P Positive supply voltage Input 6 Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2).

6 MIN MAX UNIT. Differential Input Voltage Supply Voltage Voltage at Input / Output Pin (V ) (V+) + V. + . Supply Voltage (V V ) 16 V. (3). Current at Input Pin 5 5 mA. (4) (5). Current at Output Pin 30 30 mA. Current at Power Supply Pin 40 mA. Lead Temperature (Soldering, 10 sec.) 260 C. (6). Junction Temperature 150 C. Storage temperature, Tstg 65 150 C. (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

7 (3) Limiting Input pin current is only necessary for Input voltages that exceed absolute maximum Input voltage ratings. (4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150 C. Output currents in excess of 30 mA over long term may adversely affect reliability. (5) Do not short circuit Output to V+, when V+ is greater than 13 V or reliability will be adversely affected. (6) The maximum power dissipation is a function of TJ(max), R JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) TA)/ JA. All numbers apply for packages soldered directly into a PC board. Copyright 1997 2015, Texas Instruments Incorporated Submit Documentation Feedback 3. Product Folder Links: LMC6482 .

8 LMC6482 . SNOS674E NOVEMBER 1997 REVISED APRIL 2015 ESD Ratings VALUE UNIT. V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 1500 V. (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1). MIN MAX UNIT. Supply Voltage 3 V. LMC6482AM 55 125 C. Junction Temperature Range LMC6482AI, LMC6482I 40 85 C. (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

9 Thermal Information LMC6482 LMC6482 LMC6482 . (1). THERMAL METRIC D (SOIC) DGK (VSSOP) P (PDIP) UNIT. 8 PINS 8 PINS 8 PINS. R JA Junction-to-ambient thermal resistance 155 194 90 C/W. (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Electrical Characteristics for V+ = 5 V. Unless otherwise specified, all limits specified for TJ = 25 C, V+ = 5 V, V = 0 V, VCM = VO = V+/2 and RL > 1 M. At Temperature TJ = 25 C. PARAMETER TEST CONDITIONS Extremes (1) UNIT. MIN TYP (2) MAX (3) MIN TYP (2) MAX (3). DC Electrical Characteristics LMC6482AI Input Offset VOS LMC6482I 3 mV. Voltage LMC6482M 3 TCVOS Input Offset 1. Voltage V/ C. Average Drift LMC6482AI 4. (4). IB Input Current See LMC6482I 4 pA. LMC6482M 10. LMC6482AI 2. Input Offset (4). IOS See LMC6482I 2 pA. Current LMC6482M 5.

10 CIN Common- 3. Mode Input pF. Capacitance RIN Input 10. Tera . Resistance (1) See Recommended Operating Conditions for operating temperature ranges. (2) Typical Values represent the most likely parametric norm. (3) All limits are specified by testing or statistical analysis. (4) Ensured limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value. 4 Submit Documentation Feedback Copyright 1997 2015, Texas Instruments Incorporated Product Folder Links: LMC6482 . LMC6482 . SNOS674E NOVEMBER 1997 REVISED APRIL 2015. Electrical Characteristics for V+ = 5 V (continued). Unless otherwise specified, all limits specified for TJ = 25 C, V+ = 5 V, V = 0 V, VCM = VO = V+/2 and RL > 1 M. At Temperature TJ = 25 C. PARAMETER TEST CONDITIONS Extremes (1) UNIT. MIN TYP (2) MAX (3) MIN TYP (2) MAX (3). LMC6482AI 70 82 67.