LMH1983 3G/HD/SD Video Clock Generator with …

1 LOOPFILTER27 MHz VCXOLMH1983 FPGAA/V Frame Sync with Downconverter, Audio Embedder and De-embedder1080 SDI out+ embedded audioLMH1981 Sync SeparatorH syncV sync525iAnalog ref. inF sync27 MHz (PLL1) MHz (PLL2) MHz (PLL3) MHz (PLL4)1080 SDI in + embedded audioGenlocked to Video ref. in525 SDI out + embedded Hz (TOF1) Hz (TOF2) Hz (TOF3) HzProductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityLMH1983 SNLS309I APRIL2010 REVISEDDECEMBER2014 LMH19833G/HD/SDVideo Clock Generatorwith AudioClock1 Features3 DescriptionTheLMH1983is a highly-integratedprogrammable1 FourPLLsfor SimultaneousA/V ClockGenerationaudio/ Video (A/V)clockgene ratorintendedfor PLL1:27 or can PLL2 PLL3 (SDI)and digitalaudioAES3 offers PLL4 2X(X = 0 to 15)low-jitterreferenceclocksfor any SDI transmitterto 3 x 2 VideoClockCrosspointmeetstringentoutputj itterspecificationswithoutadditionalcloc kcleaningcircuits.

2 FlexiblePLL Bandwidthto OptimizeJitterPerformanceand LockTimeTheLMH1983featuresautomaticinput format Soft Resynchronizationto NewReferencedetection,simpleprogrammingo f multipleA/V outputformats,genlockor digitalfree-runmodes,and DigitalHoldoveror Free-runon Lossof Referenceoverrideprogrammabilityof variousautomatic StatusFlagsfor Lossof Referenceand recognizedinputformatsincludeHVFPLL Locksyncsfor the majorvideostandards,27 MHz,10 V SingleSupplyOperationMHz,and 32 audiowordclocks. I2C Interfacewith AddressSelectPin (3 States)The dual-stagePLL architectureintegratesfour PLLswith first stage(PLL1)uses2 Applicationsan externallow-noise27 MHzVCXO withnarrowloopbandwidthto providea cleanreferenceclockfor TripleRate( 3G/HD/SD )SDI SerDesthe (PLL2,3, 4) FPGAR eferenceClockGeneration/Cleaningconsists of threeparallelVCOPLL sfor simultaneous AudioEmbedor De-embedgenerationof the majordigitalA/V clockfundamentalrates, , ,and (4 ).

3 EachPLLcan FrameSynchronizers(Genlock,DARS)generate a clockand a timingpulseto indicatetop of A-D or D-A Conversion,Editing,ProcessingCardsframe( TOF). Keyersand LogoInsertersDeviceInformation(1) Formator StandardsConvertersPARTNUMBERPACKAGEBODY SIZE(NOM) VideoDisplaysand ProjectorsLMH1983 WQFN(40) A/V Testand MeasurementEquipment(1) For all availablepackages,see the orderableaddendumatthe end of the IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand APRIL2010 Applicationsand Description(continued).. Pin Configurationsand Deviceand Mechanical,Packaging,and RevisionHistoryNOTE:Pagenumbersfor previousrevisionsmay differfrompagenumbersin the (October2014)to RevisionIPage (Nov2012)to RevisionHPage AddedAdded,updated,or renamedthe followingsections:DeviceInformationTable ,Pin ConfigurationandFunctions,Applicationand Implementation;PowerSupplyRecommendation s;Layout;Deviceand DocumentationSupport.

4 Mechanical,Packaging,and Changedtypicalvalueof low outputsink currentto matchsimulationvalueof Addedclarificationsectionfor Changedappearanceof Reg 0x11modedescriptionfor Changedregisterinitializationprocedureto preventdevicefromexhibitingpoorduty cycleperformanceon 19 Addedclarificationnoteabout480 ,480 ,576i/25and 576 Changeddefaultvaluefor Reg 0x11[3:2] ChangedReg 0x11[3:2]descriptionfor clarificationof TOF1_Syncbehaviordependenton 2010 2014,TexasInstrumentsIncorporatedProduct FolderLinks:LMH1983123456783029282726252 4233334353637383940 VDDVinFinVC_LPFCLKout3+CLKout4-XOin-Cbyp 2 VDDHinNO_LOCKINITFout1 GNDNO_ALIGNGNDFout2 CLKout2+SDACLKout3-CLKout4+9 SCL102221 Fout3313211121314151617181920 VDDFout4 (OSC in)VDDVDDCbyp3 CLKout2-VDDCLKout1-CLKout1+Die Attach Pad (DAP)Connect to GND on PCBADDRGNDCbyp4 VDDXOin+VDDVDDNO_REF APRIL2010 REVISEDDECEMBER20145 Description(continued)Whenlockedto reference,an internal10-bitADCwill trackthe lossofreference(LOR)occurs,the LMH1983can be programmedto holdthe controlvoltageto maintainoutputaccuracywithin ppm(typical)

5 Of the LMH1983can be configuredto re-synchronizeto a previousreferencewith Pin Configurationsand FunctionsRTA40 APackage40-PinWQFNP ackagewithExposedThermalPadTop ViewPin PLL12 VDD logicI/OHorizontalsyncreferencesignal3 HinILVCMOSA utopolaritycorrectionfor HVFwill be basedoff Hin be appliedto (odd/even)referencesignal6 INITILVCMOSR esetsignalfor audio-videophasealignment(risingedgetrig gered)I2C addressselectPin settings:7 ADDRILVCMOS Tie low: 0x65(7-bitslaveaddressin hex) Float:0x66 Tie high:0x678 SDA(1)I/OI2CI2C Datasignal9 SCL(1)II2CI2C Clocksignal10 VDD logicI/O11NO_LOCK(2)OLVCMOSL ossof lock statusflag for PLLs1-4 (activehigh)12NO_ALIGNOLVCMOSL ossof alignmentstatusflag for OUTs1 4 (activehigh)(1)SDAand SCLpins eachrequirea pull-upresistorof k to the VDDsupply.

6 (2)The NO_LOCK statusflag is derivedfromthe LockStatusregisterbits (LOCK1-4)for statusbit can be maskedfromthe NO_LOCK flag by 2010 2014,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback3 ProductFolderLinks: LMH1983 LMH1983 SNLS309I APRIL2010 Functions(continued) referencestatusflag (activehigh)14 CLKout4 AudioclockfromPLL4(fundamentalrate is ).OLVDS15 CLKout4+The outputis defaultand is selectablevia the V supplyfor CLKout4 Audioframetimingsignalfor OUT4(activelow.)TimingGeneratorfixedto outputis the audio- Video -frame(AVF)pulseby defaultand is programmablevia the (OSCin)I/OLVCMOScan be usedto applya 27 MHzexternalclockfor PLL4to generateanaudioclockindependentof the videoinputreference;this functionmustbe enabledvia the GNDG round19 VDD V supplyfor PLL3and PLL420 VDD V supplyfor CLKout321 GND GNDG roundVideoframetimingsignalfor OUT3(activelow).

7 Timinggenerator22 Fout3 OLVCMOS assignableto PLL1,PLL2,or selectablevia ,PLL2,or PLL3dependingon output23 CLKout3+ outputis defaultand is24 CLKout3 selectablevia the on-chipLDOfor PLL325 Cbyp3 AnalogConnectto F and F on-chipLDOfor PLL426 Cbyp4 AnalogConnectto F and F on-chipLDOfor PLL227 Cbyp2 AnalogConnectto F and F ,PLL2,or PLL3dependingon output28 CLKout2+ outputis defaultand is selectable29 CLKout2 via the OUT2(activelow).Timinggenerator30 Fout2 OLVCMOS assignableto PLL1,PLL2,or selectablevia CLKout232 VDD PLL227 MHzVCXO clocksignalfor (3) LVCMOS:Directlyconnectclocksignalto XOin+and bias XOin-toILVCMOS/LVDS34 XOin+mid-supplywith F bypasscapacitor.

8 LVDS:DirectlyconnectLVDS clocksignalsto XOin+and XOin-.(4)35 CLKout1 +The outputis 27 MHzby defaultand is selectablevia the OUT1(activeLow).Timing37 Fout1 OLVCMOS generatorfixedto PLL1 OUT1 Formatfollowsthe V supplyfor CLKout139 GND GNDG roundLoopfilter for PLL1chargepumpoutputwith VCXOV oltageControl(VC) free-runand holdovermode,PLL1is disabledand an internalDACoutputsa controlvoltageto the VCXO. DAP GNDDie AttachPad (Connectto groundon PCB)(3)XOinmustbe drivenby a 27 MHzclockin orderto reador writeregistersvia I2C.(4)A TCXOor otherclean27 MHzoscillatorcan be appliedfor standaloneclockgenerationusingPLLs2-4 (bypassPLL1).4 SubmitDocumentationFeedbackCopyright 2010 2014, APRIL2010 REVISEDDECEMBER20147 (unlessotherwisenoted)(1)(2)(3) (anyinput) + (anyoutput) + CTstgStoragetemperaturerange-65150 C(1)AbsoluteMaximumRatingsare limitsbeyondwhichdamageto the devicemay conditionsunderwhichoperationof the deviceis intendedto be ensuredspecificationsand test conditions,see the causepermanentdamageto the stressratingsonly,whichdo not implyfunctionaloperationof the deviceat theseor any otherconditionsbeyondthoseindicatedunder RecommendedOperatingConditions.

9 Exposureto absolute-maximum-ratedconditionsfor extendedperiodsmay affectdevicereliability.(2)For solderinginformation,see SNOA549.(3)If Military/Aerospacespecifieddevicesare required,pleasecontactthe TexasInstrumentsSalesOffice/Distributors for (HBM),per ANSI/ESDA/JEDECJS-001(1)2500 Machinemodel(MM)(2)250V(ESD)Electrostati cdischargeVCharged-devicemodel(CDM),per JEDEC specificationJESD22-750C101(3)(1)JEDEC documentJEP155statesthat 500-VHBM allowssafe manufacturingwith a than500-VHBMis possiblewith the 2500V may actuallyhavehigherperformance.(2)Machine Model,applicablestd. JESD22-A115-A(ESDMM std. of JEDEC).(3)JEDEC documentJEP157statesthat 250-VCDM allowssafe manufacturingwith a than250-VCDMis possiblewith the 750 V may (unlessotherwisenoted)MINNOMMAXUNITI nputVoltage0 VDDVT emperatureRange,TA-4085 (1)UNIT40 PINSTJMAXJ unctionTemperature, 5% C/WR JAThermalResistance(2)33 C/W(1)For moreinformationabouttraditionaland new thermalmetrics,see theIC PackageThermalMetricsapplicationreport,S PRA953.

10 (2)The maximumpowerdissipationis a functionof TJ(MAX), R JA. The maximumallowablepowerdissipationat any ambienttemperatureisPD = (TJ(MAX) TA)/ R JA. All numbersapplyfor packagessoldereddirectlyontoa PC 2010 2014,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback5 ProductFolderLinks: LMH1983 LMH1983 SNLS309I APRIL2010 (1)Unlessotherwisespecified,all limitsare specifiedfor TA= 25 C, VDD= V, RL_CLK= 100 (CLKoutdifferentialload).PARAMETERTESTCO NDITIONSMIN(2)TYP(3)MAX(2)UNITD efaultregistersettings,no load on ,PLL3and PLL4disabled,no load on (Hin,Vin, Fin)VILLow inputvoltageIIN= 10 VDDVVIHH ighinputvoltageIIN= 10 VDDVDDVT imefromwhenreferenceinputfirst presentedtowhendetectedas indicatedby stableand accurate(noFramesmissingpulses).