LMK00338 8-Output PCIe Gen1/2/3 Clock Buffer and Level ...

1 CLKoutA_ENCLKoutB_ENCopyright 2017, Texas Instruments IncorporatedProductFolderOrderNowTechnic alDocumentsTools &SoftwareSupport &CommunityAn IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand DECEMBER2013 REVISEDJUNE2017 LMK003388-OutputDifferentialClock Bufferand Level Translator11 Features1 3:1 InputMultiplexer Two UniversalInputsOperateup to 400 MHzand AcceptLVPECL,LVDS,CML,SSTL,HSTL,HCSL,or Single-EndedClocks One CrystalInputAcceptsa 10-MHzto 40-MHzCrystalor Single-EndedClock Two BanksWith4 DifferentialOutputsEach HCSL,or Hi-Z (Selectableper Bank) AdditiveRMSP haseJitterfor PCIeGen3at100 MHz: 30 fs RMS(Typical) 72 dBc at LVCMOSO utputWithSynchronousEnableInput Pin-ControlledConfiguration V 5% 3 5% IndustrialTemperatureRange.

2 40 C to +85 C 40-leadWQFN(6 mm 6 mm)2 Applications ClockDistributionand LevelTranslationfor ADCs,DACs,Multi-GigabitEthernet,XAUI,Fib reChannel,SATA/SAS,SONET/SDH,CPRI,High-F requencyBackplanes Switches,Routers,Line Cards,TimingCards Servers,Computing,PCI Express( ) RemoteRadioUnitsand BasebandUnits3 DescriptionTheLMK00338deviceis an8-outputPCIeGen1/Gen2/Gen3fanoutbuffer intendedfor high-frequency,low-jitterclock,datadistr ibution,and inputclockcan be selectedfromtwouniversalinputsor distributedto two banksof 4 a synchronousenableinputfor runt-pulse-freeoperationwhenenabledor ,versatility,and powerefficiency,makingit idealforreplacingfixed-outputbufferdevic eswhileincreasingtimingmarginin the (1)PARTNUMBERPACKAGEBODYSIZE(NOM)LMK0033 8 WQFN(40) (1)

3 For all availablepackages,see the orderableaddendumatthe end of the DECEMBER2013 : LMK00338 SubmitDocumentationFeedbackCopyright 2013 2017,TexasInstrumentsIncorporatedTableof Contents1 Pin Configurationand 118 Applicationand Deviceand Mechanical,Packaging,and RevisionHistoryNOTE:Pagenumbersfor previousrevisionsmay differfrompagenumbersin the (October2014)to RevisionBPage ChangedCLKoutA_ENand CLKoutB_ENpins to CLKoutA_ENand CLKoutB_ENthroughoutthe AddedReceivingNotificationof (December2013)to RevisionAPage Added,updated,or renamedthe followingsections:DeviceInformationTable ,Applicationand Implementation;PowerSupplyRecommendation s;Layout;Deviceand DocumentationSupport;Mechanical,Packagin g, Changed1 MHzto 12 kHz.

4 7 *CLKoutB1 CLKoutB0*GNDCLKin1*REFout_ENCLKoutA0*VCC OACLKoutA1 CLKoutA1*CLKoutA2 CLKoutA2*CLKoutA3 CLKoutA3*CLKoutA_ENVCCOSCoutCLKin0 CLKin0*CLKoutB_ENGNDCLKoutB3*CLKoutB2*CL KoutB2 VCCOBVCCOBCLKoutB0 CLKin1 VCCREFoutVCCOCGND39403837363534333231109 8765432112111314151617181920212223242526 27282930 DAPTop Down DECEMBER2013 REVISEDJUNE2017 ProductFolderLinks: LMK00338 SubmitDocumentationFeedbackCopyright 2013 2017,TexasInstrumentsIncorporated(1)Any unusedoutputpins shouldbe left floatingwith minimumcopperlength(seenoteinClockOutput s), or properlyterminatedifconnectedto a transmissionline, or disabled/Hi-Zif outputconfigurationorTerminationand Use ofClockDriversoutputinterfaceand terminationtechniques.

5 (2)CMOS controlinputwith Pin Configurationand FunctionsRTAP ackage40-PinWQFNTop ViewPin Functions(1) the PCBgroundplanefor (differential/single-ended)CLKin0*17 IUniversalclockinput0 (differential/single-ended)CLKin134 IUniversalclockinput1 (differential/single-ended)CLKin1*33 IUniversalclockinput1 (differential/single-ended)CLKoutA_EN11 IBankA low activeoutputbufferenable(2) * * * * low activeoutputbufferenable(2) * DECEMBER2013 : LMK00338 SubmitDocumentationFeedbackCopyright 2013 2017,TexasInstrumentsIncorporatedPin Functions(1)(continued)PINTYPEDESCRIPTIO NNAMENO.

6 (3)The outputsupplyvoltages/pins(VCCOA, VCCOB, and VCCOC) is referredto generallyas VCCO whenno distinctionis needed,or whentheoutputsupplycan be inferredby the * * * (2)CLKin_SEL118 IClockinputselectionpins(2)GND20, 31,40 GNDG roundOSCin13 IInputfor also be drivenby a XO, TCXO,or OSCinis drivenby a pullingREFout_ENpin internallysynchronizedto selectedclockinput.(2)VCC12, 32,35, 39 PWRP owersupplyfor Coreand a uF low-ESRcapacitorplacedvery closeto eachVcc , 6 PWRP owersupplyfor BankA V or V. TheVCCOA pins are internallytied a uF low-ESRcapacitorplacedvery closeto eachVCCOpin.

7 (3)VCCOB25, 28 PWRP owersupplyfor BankB V or V. TheVCCOB pins are internallytied a uF low-ESRcapacitorplacedvery closeto eachVCCOpin.(3)VCCOC37 PWRP owersupplyfor V or V. Bypasswith a uF low-ESRcapacitorplacedvery closeto eachVCCOpin.(3) DECEMBER2013 REVISEDJUNE2017 ProductFolderLinks: LMK00338 SubmitDocumentationFeedbackCopyright 2013 2017,TexasInstrumentsIncorporated(1)Stre ssesbeyondthoselistedunderAbsoluteMaximu mRatingsmay causepermanentdamageto the stressratingsonly,whichdo not implyfunctionaloperationof the deviceat theseor any otherconditionsbeyondthoseindicatedunder RecommendedOperatingConditions.

8 Exposureto absolute-maximum-ratedconditionsfor extendedperiodsmay affectdevicereliability.(2)If Military/Aerospacespecifieddevicesare required,pleasecontactthe TexasInstrumentsSalesOffice/Distributors for (unlessotherwisenoted)(1)(2)MINMAXUNITVC C,VCCOS upplyvoltages (VCC+ )VTLL eadtemperature(solder4 s)260 CTJJ unctiontemperature150 CTstgStoragetemperature 65150 C(1)JEDEC documentJEP155statesthat 500-VHBM allowssafe manufacturingwith a standardESDcontrolprocess.(2)JEDEC documentJEP157statesthat 250-VCDM allowssafe manufacturingwith a (ESD)ElectrostaticdischargeHuman-bodymod el(HBM),per ANSI/ESDA/JEDECJS-001(1) 2000 VCharged-devicemodel(CDM),per JEDEC specificationJESD22-C101(2) 750 Machinemodel(MM) 150(1)The outputsupplyvoltages/pins(VCCOA, VCCOB, and VCCOC) will be referredto generallyas VCCO whenno distinctionis needed,orwhenthe outputsupplycan be inferredby the outputbank/type.

9 (2)VCCO shouldbe less thanor equalto VCC(VCCO VCC). 402585 CTJJ unctiontemperature125 (1) (2) 5% + 5% 5% + 5%(1)For moreinformationabouttraditionaland new thermalmetrics,see theIC PackageThermalMetricsapplicationreport.( 2)Specificationassumes9 thermalvias connectthe die attachpad (DAP)to the embeddedcopperplaneon the play a key role in improvingthe thermalperformanceof the recommendsusingthe maximumnumberof vias inthe (1) LMK00338 UNITRTA(WQFN)40 PINS(2)R C/WR JC(top)Junction-to-case(top) (DAP) C/W6 LMK00338 SNAS636B DECEMBER2013 : LMK00338 SubmitDocumentationFeedbackCopyright 2013 2017,TexasInstrumentsIncorporated(1)The outputsupplyvoltages/pins(VCCOA, VCCOB, and VCCOC) will be referredto generallyas VCCO whenno distinctionis needed,orwhenthe outputsupplycan be inferredby the outputbank/type.

10 (2)TheElectricalCharacteristicstableslis t ensuredspecificationsunderthe listedRecommendedOperatingConditionsexce ptasotherwisemodifiedor specifiedby theElectricalCharacteristicsconditionsan d estimationsonly and arenot ensured.(3)SeePowerSupplyRecommendations for moreinformationon currentconsumptionand powerdissipationcalculations.(4)Powersup plyripplerejection,or PSRR,is definedas the single-sidebandphasespurlevel(in dBc)modulatedontothe clockoutputwhena single-tonesinusoidalsignal(ripple)is injectedontothe amplitudemodulationeffectsand smallindexmodulation,the peak-to-peakdeterministicjitter (DJ) can be calculatedusingthe measuredsingle-sidebandphasespurlevel(PS RR)as follows:DJ (ps pk-pk)= [ (2 10(PSRR/ 20)) / ( fCLK) ] 1E12(5)Specificationis ensuredby characterizationand is not testedin production.