Low-density access line, ARM®-based 32 bit MCU with 16 or ...

1 This is information on a product in full production. September 2015 DocID15058 Rev 61/87 STM32F101x4 STM32F101x6 Low-density access line, ARM -based 32 bit MCU with 16 or 32 KB Flash, 5 timers, ADC and 4 communication interfacesDatasheet - production dataFeatures Core: ARM 32-bit Cortex -M3 CPU 36 MHz maximum frequency, DMIPS/MHz (Dhrystone ) performance at 0 wait state memory access Single-cycle multiplication and hardware division Memories 16 to 32 Kbytes of Flash memory 4 to 6 Kbytes of SRAM Clock, reset and supply management to V application supply and I/Os POR, PDR and programmable voltage detector (PVD) 4-to-16 MHz crystal oscillator Internal 8 MHz factory-trimmed RC Internal 40 kHz RC PLL for CPU clock 32 kHz oscillator for RTC with calibration Low power Sleep, Stop and Standby modes VBAT supply for RTC and backup registers Debug mode Serial wire debug (SWD) and JTAG interfaces DMA 7-channel DMA controller Peripherals supported.

2 Timers, ADC, SPIs, I2Cs and USARTs 1 12-bit, 1 s A/D converter (up to 16 channels) Conversion range: 0 to V Temperature sensor Up to 51 fast I/O ports 26/37/51 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant Up to 5 timers Up to two16-bit timers, each with up to 4 IC/OC/PWM or pulse counter 2 watchdog timers (Independent and Window) SysTick timer: 24-bit downcounter Up to 4 communication interfaces 1 x I2C interface (SMBus/PMBus) Up to 2 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) 1 SPI (18 Mbit/s) CRC calculation unit, 96-bit unique ID ECOPACK packages Table 1. Device summary ReferencePart numberSTM32F101x4 STM32F101C4, STM32F101R4, STM32F101T4 STM32F101x6 STM32F101C6, STM32F101R6, STM32F101T6 LQFP487 x 7 mmLQFP6410 x 10 mmVFQFPN366 6 , STM32F101x62/87 DocID15058 Rev 6 Contents1 Introduction.

3 92 Description .. overview .. compatibility throughout the family .. Cortex -M3 core with embedded Flash and SRAM .. Flash memory .. (cyclic redundancy check) calculation unit .. SRAM .. vectored interrupt controller (NVIC) .. interrupt/event controller (EXTI) .. and startup .. modes .. supply schemes .. supply supervisor .. regulator .. modes .. (real-time clock) and backup registers .. watchdog .. watchdog .. timer .. timers (TIMx) .. C bus .. synchronous/asynchronous receiver transmitter (USART) .. peripheral interface (SPI) .. (general-purpose inputs/outputs) .. (analog to digital converter) .. sensor .. wire JTAG debug port (SWJ-DP) .. 203 Pinouts and pin description .. 21 DocID15058 Rev 63/87 STM32F101x4, STM32F101x6 Contents44 Memory mapping.

4 275 Electrical characteristics .. conditions .. and maximum values .. values .. curves .. capacitor .. input voltage .. supply scheme .. consumption measurement .. maximum ratings .. conditions .. operating conditions .. conditions at power-up / power-down .. reset and power control block characteristics .. reference voltage .. current characteristics .. clock source characteristics .. clock source characteristics .. characteristics .. characteristics .. characteristics .. maximum ratings (electrical sensitivity) .. current injection characteristics .. port characteristics .. pin characteristics .. timer characteristics .. interfaces .. ADC characteristics .. sensor characteristics .. 706 Package characteristics.

5 Mechanical data .. package information .. package information .. 75 ContentsSTM32F101x4, STM32F101x64/87 DocID15058 Rev package information .. characteristics .. document .. the maximum junction temperature for an application .. 837 Ordering information scheme .. 848 Revision history .. 85 DocID15058 Rev 65/87 STM32F101x4, STM32F101x6 List of Tables6 List of TablesTable summary .. 1 Table STM32F101xx device features and peripheral counts .. 11 Table family .. 14 Table STM32F101xx pin definitions .. 23 Table characteristics .. 30 Table characteristics .. 31 Table characteristics.. 31 Table operating conditions .. 31 Table conditions at power-up / power-down .. 32 Table reset and power control block characteristics.. 33 Table internal reference voltage.

6 34 Table current consumption in Run mode, code with data processing running from Flash .. 35 Table current consumption in Run mode, code with data processing running from RAM.. 35 Table current consumption in Sleep mode, code running from Flash or RAM .. 37 Table and maximum current consumptions in Stop and Standby modes .. 37 Table current consumption in Run mode, code with data processing running from Flash .. 40 Table current consumption in Sleep mode, code running from Flash or RAM .. 41 Table current consumption .. 42 Table external user clock characteristics.. 43 Table external user clock characteristics .. 43 Table 4-16 MHz oscillator characteristics.. 45 Table oscillator characteristics (fLSE = kHz) .. 46 Table oscillator characteristics.. 47 Table oscillator characteristics.

7 48 Table mode wakeup timings .. 48 Table characteristics .. 48 Table memory characteristics .. 49 Table characteristics .. 50 Table characteristics .. 50 Table absolute maximum ratings .. 51 Table sensitivities .. 51 Table current injection susceptibility .. 52 Table static characteristics .. 53 Table voltage characteristics .. 56 Table AC characteristics .. 57 Table pin characteristics .. 58 Table characteristics .. 60 Table characteristics.. 61 Table frequency (fPCLK1= MHz, VDD_I2C = V) .. 62 Table characteristics .. 63 Table characteristics .. 66 Table max for fADC = 14 MHz .. 67 Table accuracy - limited test conditions .. 67 Table accuracy .. 68 List of TablesSTM32F101x4, STM32F101x66/87 DocID15058 Rev 6 Table characteristics .. 70 Table - 36-pin, 6x6 mm, mm pitch very thin profile fine pitch quad flat package mechanical data.

8 72 Table - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data .. 75 Table - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data .. 79 Table thermal characteristics .. 82 Table information scheme .. 84 Table revision history .. 85 DocID15058 Rev 67/87 STM32F101x4, STM32F101x6 List of Figures8 List of FiguresFigure Low-density access line block diagram .. 12 Figure tree .. 13 Figure Low-density access line LQFP64 pinout .. 21 Figure Low-density access line LQFP48 pinout .. 21 Figure Low-density access line UFQPFN48 pinout .. 22 Figure Low-density access line VFQPFN36 pinout .. 22 Figure map .. 27 Figure loading conditions .. 29 Figure input voltage .. 29 Figure supply scheme.. 29 Figure consumption measurement scheme .. 30 Figure current consumption in Run mode versus frequency (at V) - code with data processing running from RAM, peripherals enabled.

9 36 Figure current consumption in Run mode versus frequency (at V) - code with data processing running from RAM, peripherals disabled .. 36 Figure current consumption on VBAT with RTC on versus temperature at different VBAT values .. 38 Figure current consumption in Stop mode with regulator in Run mode versus temperature at VDD = V and V .. 38 Figure current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = V and V .. 39 Figure current consumption in Standby mode versus temperature at VDD = V and V .. 39 Figure external clock source AC timing diagram .. 44 Figure external clock source AC timing diagram .. 44 Figure application with an 8 MHz crystal .. 45 Figure application with a kHz crystal .. 47 Figure I/O input characteristics - CMOS port.

10 54 Figure I/O input characteristics - TTL port .. 54 Figure V tolerant I/O input characteristics - CMOS port .. 55 Figure V tolerant I/O input characteristics - TTL port .. 55 Figure AC characteristics definition .. 58 Figure NRST pin protection .. 59 Figure bus AC waveforms and measurement circuit(1) .. 62 Figure timing diagram - slave mode and CPHA = 0 .. 64 Figure timing diagram - slave mode and CPHA = 1(1) .. 64 Figure timing diagram - master mode(1) .. 65 Figure accuracy characteristics .. 68 Figure connection diagram using the ADC .. 69 Figure supply and reference decoupling .. 69 Figure - 36-pin, 6x6 mm, mm pitch very thin profile fine pitch quad flat package outline .. 71 Figure - 36-pin, 6x6 mm, mm pitch very thin profile fine pitch quad flat package recommended footprint.