LP62S16256G-T - AMIC TECHNOLOGY

1 LP62S16256G-T Series Preliminary 256K X 16 BIT LOW VOLTAGE CMOS SRAM. Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM. Revision History Rev. No. History Issue Date Remark Initial issue June 6, 2006 Preliminary Change temperature from 0 C-70 C to -10 C-70 C November 17, 2006. PRELIMINARY (November, 2006, Version ) AMIC TECHNOLOGY , Corp. LP62S16256G-T Series Preliminary 256K X 16 BIT LOW VOLTAGE CMOS SRAM. Features General Description Operating voltage: to The LP62S16256G-T is a low operating current 4,194,304-bit Access times: 55ns / 70ns (max.) static random access memory organized as 262,144 words Current: by 16 bits and operates on low power voltage from to Very low power version: Operating: 40mA (max.) It is built using AMIC's high performance CMOS. Standby: 10 A (max.) process. Full static operation, no clock or refreshing required Inputs and three-state outputs are TTL compatible and allow All inputs and outputs are directly TTL-compatible for direct interfacing with common system bus structures.

2 Common I/O using three-state output The chip enable input is provided for POWER-DOWN, device Data retention voltage: (min.) enable. Two byte enable inputs and an output enable input Available in 44-pin TSOP and 48-ball CSP (6 8mm) are included for easy interfacing. packages Data retention is guaranteed at a power supply voltage as low All Pb-free (Lead-free) products are RoHS compliant as Product Family Power Dissipation Operating VCC Package Product Family Speed Data Retention Standby Operating Temperature Range Type (ICCDR, Typ.) (ISB1, Typ.) (ICC2, Typ.). 44L TSOP. LP62S16256G-T -10 C ~ +70 C ~ 55ns / 70ns A 1 A 48B CSP. 1. Typical values are measured at VCC = , TA = 25 C and not 100% tested. 2. Data retention current VCC = Pin Configurations TSOP CSP (Chip Size Package). 48-pin Top View A4 1 44 A5.

3 A3 2 43 A6. A2 3 42 A7 1 2 3 4 5 6. A1 4 41 OE. A LB OE A0 A1 A2 NC. LP62S16256GV-T. A0 5 40 HB. CE 6 39 LB. I/O1 7 38 I/O16. B I/O9 HB A3 A4 CE I/O1. I/O2 8 37 I/O15. I/O3 9 36 I/O14. C I/O10 I/O11 A5 A6 I/O2 I/O3. I/O4 10 35 I/O13 GN. VCC 11 34 GND. D I/O12 A17 A7 I/O4 VCC. D. GND 12 33 VCC GN. I/O5 13 32 I/O12. E VCC I/O13 NC A16 I/O5 D. I/O6 14 31 I/O11. I/O7 15 30 I/O10. F I/O15 I/O14 A14 A15 I/O6 I/O7. I/O8 16 29 I/O9. WE 17 28 NC. G I/O16 NC A12 A13 WE I/O8. A17 18 27 A8. A16 19 26 A9. H NC A8 A9 A10 A11 NC. A15 20 25 A10. A14 21 24 A11. A13 22 23 A12. PRELIMINARY (November, 2006, Version ) 1 AMIC TECHNOLOGY , Corp. LP62S16256G-T Series Block Diagram VCC. A0. GND. 512 X 8192. DECODER. MEMORY ARRAY. A16. A17. I/O1 I/O9. COLUMN I/O. INPUT. INPUT. DATA DATA. CIRCUIT. CIRCUIT. I/O8 I/O16. CE.

4 LB CONTROL. HB. CIRCUIT. OE. WE. Pin Descriptions -- TSOP. Pin No. Symbol Description 1 - 5, 18 - 27, 42 - 44 A0 - A17 Address Inputs 6 CE Chip Enable Input 7 - 10, 13 - 16, 29 - 32, 35 - 38 I/O1 - I/O16 Data Inputs/Outputs 17 WE Write Enable Input 39 LB Lower Byte Enable Input (I/O1 to I/O8). 40 HB Higher Byte Enable Input (I/O9 to I/O16). 41 OE Output Enable Input 11, 33 VCC Power 12, 34 GND Ground 28 NC No Connection PRELIMINARY (November, 2006, Version ) 2 AMIC TECHNOLOGY , Corp. LP62S16256G-T Series Pin Description - CSP. Symbol Description Symbol Description A0 - A17 Address Inputs HB Higher Byte Enable Input (I/O9 - I/O16). CE Chip Enable OE Output Enable I/O1 - I/O16 Data Input/Output VCC Power Supply WE Write Enable Input GND Ground LB Byte Enable Input NC No Connection (I/O1 - I/O8). Recommended DC Operating Conditions (TA = -10 C to +70 C).

5 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 3 V. GND Ground 0 0 0 V. VIH Input High Voltage - VCC + V. VIL Input Low Voltage - + V. CL Output Load - - 30 pF. TTL Output Load - - 1 - PRELIMINARY (November, 2006, Version ) 3 AMIC TECHNOLOGY , Corp. LP62S16256G-T Series Absolute Maximum Ratings* *Comments VCC to GND .. to + Stresses above those listed under "Absolute Maximum IN, IN/OUT Volt to to VCC + Ratings" may cause permanent damage to this device. Operating Temperature, Topr ..-10 C to +70 C These are stress ratings only. Functional operation of this Storage Temperature, C to +125 C device at these or any other conditions above those Power Dissipation, indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

6 DC Electrical Characteristics (TA = -10 C to +70 C, VCC = to , GND = 0V). Symbol Parameter LP62S16256G-55 LLT / 70 LLT Unit Conditions Min. Typ. Max. ILI Input Leakage Current - - 1 A VIN = GND to VCC. CE = VIH. ILO Output Leakage Current - - 1 A HB = VIH or OE = VIH or WE = VIH. VI/O = GND to VCC. ICC Active Power Supply Current - - 5 mA CE = VIL, II/O = 0mA. ICC1 - 25 40 mA Min. Cycle, Duty = 100%. CE = VI, II/O = 0mA. Dynamic Operating Current CE = VIL, VIH = VCC, ICC2 - 8 mA. VIL = 0V, f = 1 MHz, II/O = 0 mA. ISB - - 1 mA VCC CE = VIH. Standby Current VCC ISB1 - 1 10 A. CE VCC - , VIN 0V. VOL Output Low Voltage - - V IOL = mA. VOH Output High Voltage - - V IOH = mA. PRELIMINARY (November, 2006, Version ) 4 AMIC TECHNOLOGY , Corp. LP62S16256G-T Series Truth Table CE OE WE LB HB I/O1 to I/O8 Mode I/O9 to I/O16 Mode VCC Current H X X X X Not selected Not selected ISB1, ISB.

7 X X X H H High - Z High - Z ISB1, ISB. L L Read Read ICC1, ICC2, ICC. L L H L H Read High - Z ICC1, ICC2, ICC. H L High - Z Read ICC1, ICC2, ICC. L L Write Write ICC1, ICC2, ICC. L X L L H Write High - Z ICC1, ICC2, ICC. H L High - Z Write ICC1, ICC2, ICC. L H H L X High - Z High - Z ICC1, ICC2, ICC. L H H X L High - Z High - Z ICC1, ICC2, ICC. Note: X = H or L. Capacitance (TA = 25 C, f = ). Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF VIN = 0V. CI/O* Input/Output Capacitance 8 pF VI/O = 0V. * These parameters are sampled and not 100% tested. PRELIMINARY (November, 2006, Version ) 5 AMIC TECHNOLOGY , Corp. LP62S16256G-T Series AC Characteristics (TA = -10 C to +70 C, VCC = to ). Symbol Parameter LP62S16256G-55 LLT LP62S16256G-70 LLT Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 55 - 70 - ns tAA Address Access Time - 55 - 70 ns tACE Chip Enable Access Time - 55 - 70 ns tBE Byte Enable Access Time - 55 - 70 ns tOE Output Enable to Output Valid - 30 - 35 ns tCLZ Chip Enable to Output in Low Z 10 - 10 - ns tBLZ Byte Enable to Output in Low Z 10 - 10 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ Chip Disable to Output in High Z - 20 - 25 ns tBHZ Byte Disable to Output in High Z - 20 - 25 ns tOHZ Output Disable to Output in High Z - 20 - 25 ns tOH Output Hold from Address Change 5 - 5 - ns Write Cycle tWC Write Cycle Time 55 - 70 - ns tCW Chip Enable to End of Write 50 - 60 - ns tBW Byte Enable to End of Write 50 - 60 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 50 - 60 - ns tWP Write Pulse Width 40.

8 50 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z - 25 - 25 ns tDW Data to Write Time Overlap 25 - 30 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. PRELIMINARY (November, 2006, Version ) 6 AMIC TECHNOLOGY , Corp. LP62S16256G-T Series Timing Waveforms Read Cycle 1(1, 2, 4). tRC. Address tAA. tOH. tOH. DOUT. Read Cycle 2(1, 2, 3). tRC. Address tAA. CE. tACE. tCHZ5. tCLZ5. HB, LB tBE. tBLZ5 tBHZ5. OE. tOE tOHZ5. tOLZ5. DOUT. Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low.

9 4. OE = VIL. 5. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (November, 2006, Version ) 7 AMIC TECHNOLOGY , Corp. LP62S16256G-T Series Timing Waveforms (continued). Write Cycle 1. (Write Enable Controlled). tWC. Address tAW tWR3. tCW. CE. tBW. HB, LB. tAS1 tWP2. WE. tDW tDH. DATA IN. tWHZ4. tOW. DATA OUT. Write Cycle 2. (Chip Enable Controlled). tWC. Address tAW. tWR3. tAS1 tCW2. CE. tBW. HB, LB. tWP. WE. tDW tDH. DATA IN. tWHZ4. tOW. DATA OUT. PRELIMINARY (November, 2006, Version ) 8 AMIC TECHNOLOGY , Corp. LP62S16256G-T Series Timing Waveforms (continued). Write Cycle 3. (Byte Enable Controlled). tWC. Address tAW. tCW. CE. tWR3. tAS1 tBW2. HB, LB. tWP. WE. tDW tDH. DATA IN. tWHZ4. tOW. DATA OUT. Notes: 1. tAS is measured from the address valid to the beginning of Write.

10 2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and , or LB ). 3. tWR is measured from the earliest of CE or WE or ( HB and , or LB ) going high to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (November, 2006, Version ) 9 AMIC TECHNOLOGY , Corp. LP62S16256G-T Series AC Test Conditions Input Pulse Levels to Input Rise And Fall Time 5 ns Input and Output Timing Reference Levels Output Load See Figures 1 and 2. TTL TTL. CL CL. 30pF 5pF. * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW. Data Retention Characteristics (TA = -10 C to +70 C). Symbol Parameter Min. Typ.