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MCP4728 - 12-Bit, Quad Digital-to-Analog Converter with ...

2010 Microchip Technology 1 MCP4728 Features 12-Bit Voltage Output DAC with Four Buffered Outputs On-Board Nonvolatile Memory (EEPROM) for DAC Codes and I2C Address Bits Internal or External Voltage Reference Selection Output Voltage Range:- Using Internal VREF ( ) to with Gain Setting = to with Gain Setting = 2- Using External VREF (VDD): to VDD Least Significant Bit (LSB) Differential Nonlinearity (DNL) (typical) Fast Settling Time: 6 s (typical) Normal or power -Down Mode Low power Consumption Single-Supply Operation: to I2C Interface:- Address bits: User Programmable to EEPROM - Standard (100 kbps), Fast (400 kbps) and High Speed (HS) Mode ( Mbps) 10-Lead MSOP Package Extended Temperature Range: -40 C to +125 CApplications Set Point or Offset Adjustment Sensor Calibration Closed-Loop Servo Control Low power Portable instrumentation PC Peripherals Programmable Voltage and Current Source Industrial Process Control instrumentation Bias Voltage Adjustment for power AmplifiersDescriptionThe MCP4728 device is a quad, 12-bit voltage outputDigital-to-Analog Convertor (DAC) with nonvol

Aug 04, 2010 · • Low Power Portable Instrumentation • PC Peripherals • Programmable Voltage and Current Source • Industrial Process Control • Instrumentation • Bias Voltage Adjustment for Power Amplifiers Description The MCP4728 device is a quad, 12-bit voltage output Digital-to-Analog Convertor (DAC) with nonvolatile memory (EEPROM).

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Transcription of MCP4728 - 12-Bit, Quad Digital-to-Analog Converter with ...

1 2010 Microchip Technology 1 MCP4728 Features 12-Bit Voltage Output DAC with Four Buffered Outputs On-Board Nonvolatile Memory (EEPROM) for DAC Codes and I2C Address Bits Internal or External Voltage Reference Selection Output Voltage Range:- Using Internal VREF ( ) to with Gain Setting = to with Gain Setting = 2- Using External VREF (VDD): to VDD Least Significant Bit (LSB) Differential Nonlinearity (DNL) (typical) Fast Settling Time: 6 s (typical) Normal or power -Down Mode Low power Consumption Single-Supply Operation: to I2C Interface:- Address bits: User Programmable to EEPROM - Standard (100 kbps), Fast (400 kbps) and High Speed (HS) Mode ( Mbps) 10-Lead MSOP Package Extended Temperature Range: -40 C to +125 CApplications Set Point or Offset Adjustment Sensor Calibration Closed-Loop Servo Control Low power Portable instrumentation PC Peripherals Programmable Voltage and Current Source Industrial Process Control instrumentation Bias Voltage Adjustment for power AmplifiersDescriptionThe MCP4728 device is a quad, 12-bit voltage outputDigital-to-Analog Convertor (DAC) with nonvolatilememory (EEPROM).

2 Its on-board precision outputamplifier allows it to achieve rail-to-rail analog DAC input codes, device configuration bits, andI2C address bits are programmable to the nonvolatilememory (EEPROM) by using I2C serial interfacecommands. The nonvolatile memory feature enablesthe DAC device to hold the DAC input codes duringpower-off time, allowing the DAC outputs to beavailable immediately after power -up with the savedsettings. This feature is very useful when the DACdevice is used as a supporting device for other devicesin the application s MCP4728 device has a high precision internalvoltage reference (VREF = ). The user can selectthe internal reference or external reference (VDD) foreach channel channel can be operated in Normal mode orPower-Down mode individually by setting theconfiguration register bits.

3 In power -Down mode, mostof the internal circuits in the powered down channel areturned off for power savings, and the output amplifiercan be configured to present a known low, medium, orhigh resistance output MCP4728 device includes a power -on Reset(POR) circuit to ensure reliable power -up and anon-board charge pump for the EEPROM MCP4728 has a two-wire I2C compatible serialinterface for standard (100 kHz), fast (400 kHz), or highspeed ( MHz) MCP4728 DAC is an ideal device for applicationsrequiring design simplicity with high precision, and forapplications requiring the DAC device settings to besaved during power -off MCP4728 device is available in a 10-lead MSOP package and operates from a single to , Quad Digital-to-Analog Converter with EEPROM MemoryMCP4728DS22187E-page 2 2010 Microchip Technology TypeFunctional Block Diagram123410678 VDDSCLSDAVSSVOUTDVOUTCLDACRDY/BSY95 VOUTBVOUTAMCP4728 MSOPVDDVSSSCLSDAVOUTALDACINPUTREGISTER AINPUTREGISTER BINPUTREGISTER CINPUTREGISTER DOUTPUTREGISTER ASTRING DAC A EEPROM C EEPROM D EEPROM B EEPROM APower Down ControlSTRING DAC BSTRING DAC CSTRING DAC DOutput LogicOPAMP A VOUTBP ower Down ControlOutput LogicVOUTCP ower Down ControlOutput LogicVOUTDP ower Down ControlOutput Logic Gain Control Gain Control Gain Control Gain Control VREFAVREFBVREFCVREFDVREF SelectorVREFI nternal VREF( ) RDY/BSYI2C Interface LogicVDD(VREFA, VREFB, VREFC, VREFD)

4 OUTPUTREGISTER BOUTPUTREGISTER COUTPUTREGISTER DOPAMP B OPAMP C OPAMP D UDACUDACUDACUDAC 2010 Microchip Technology CHARACTERISTICSA bsolute Maximum Ratings inputs and outputs to VDD+ at Input Pins .. 2 mACurrent at Supply Pins .. 110 mACurrent at Output Pins .. 25 mAStorage Temperature ..-65 C to +150 CAmbient Temp. with power Applied ..-55 C to +125 CESD protection on all pins .. 4 kV HBM, 400V MMMaximum Junction Temperature (TJ) .. +150 C Notice: Stresses above those listed under Maximumratings may cause permanent damage to the device. This isa stress rating only and functional operation of the device atthese or any other conditions above those indicated in theoperation listings of this specification is not implied. Exposureto maximum rating conditions for extended periods may affectdevice CHARACTERISTICSE lectrical Specifications: Unless otherwise indicated, all parameters apply at VDD= + to , VSS=0V,RL=5k , CL= 100 pF, GX=1, TA= -40 C to +125 C.

5 Typical values are at +25 C, VIH=VDD, VIL=VSS. ParameterSymbolMinTypicalMaxUnitsConditi onsPower Requirements Operating V Supply Current with External Reference(VREF=VDD)(Note 1)IDD_EXT 8001400 A VREF=VDD, VDD= 4 channels are in Normal mode. 600 A 3 channels are in Normal mode,1 channel is powered down. 400 A2 channels are in Normal mode,2 channel are powered down. 200 A 1 channel is in Normal mode,3 channels are powered Current with External ReferenceIPD_EXT 40 nA All 4 channels are powered down.(VREF=VDD)Supply Current with Internal Reference (VREF = Internal)(Note 1)IDD_INT 8001400 AVREF= Internal ReferenceVDD= 4 channels are in normal mode. 600 A 3 channels are in Normal mode,1 channel is powered down. 400 A2 channels are in Normal mode,2 channels are powered down.

6 200 A 1 channel is in Normal mode,3 channels are powered Current with Internal Reference IPD_INT 4560 A All 4 channels are powered Internal ReferenceNote 1:All digital input pins (SDA, SCL, LDAC) are tied to High , Output pins are unloaded, code = 0 x :The power -up ramp rate measures the rise of VDD over :This parameter is ensured by design and not 100% :This parameter is ensured by characterization and not 100% :Test code range: 100 - 4000 codes, VREF = VDD, VDD = :Time delay to settle to a new reference when switching from external to internal reference or vice :This parameter is indirectly tested by Offset and Gain error :Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full :This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT.

7 This time delay is not included in the output settling time 4 2010 Microchip Technology Reset Threshold VoltageVPOR VAll circuits, including EEPROM, are ready to Ramp RateVRAMP1 V/sNote 2, Note 4DC Accuracy Resolution n12 Bits Code Change: 000h to FFFh Integral Nonlinearity (INL) Error INL 2 13 LSB Note 5 DNL ErrorDNL LSB Note 5 Offset Error VOS 5 20mVCode = 000h See Figure 2-24 Offset Error Drift VOS/ C ppm/ C -45 C to +25 C ppm/ C +25 C to +125 CGain Error GE + of FSR Code = FFFh, Offset error is not value is at room temperatureSee Figure 2-25 Gain Error Drift GE/ C -3 ppm/ C Internal Voltage Reference (VREF), (Note 3)

8 Internal Voltage Reference VREF V Temperature Coefficient VREF/ C 125 ppm/ C -40 to 0 C LSB/ C 45 ppm/ C 0 to +125 C LSB/ CReference Output NoiseENREF 290 Vp-p Code = FFFh, 10 Hz, Gx=1 Output Noise DensityeNREF Code = FFFh, 1 kHz, Gx=1 Code = FFFh, 10 kHz, Gx=11/f Corner Frequency fCORNER 400 Hz ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD= + to , VSS=0V,RL=5k , CL= 100 pF, GX=1, TA= -40 C to +125 C. Typical values are at +25 C, VIH=VDD, VIL=VSS. ParameterSymbolMinTypicalMaxUnitsConditi onsNote 1:All digital input pins (SDA, SCL, LDAC) are tied to High , Output pins are unloaded, code = 0 x :The power -up ramp rate measures the rise of VDD over :This parameter is ensured by design and not 100% :This parameter is ensured by characterization and not 100% :Test code range: 100 - 4000 codes, VREF = VDD, VDD = :Time delay to settle to a new reference when switching from external to internal reference or vice :This parameter is indirectly tested by Offset and Gain error :Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full :This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT.

9 This time delay is not included in the output settling time V 2010 Microchip Technology 5 MCP4728 Analog Output (Output amplifier )Output Voltage Swing VOUT FSR V Note 7 Full Scale Range(Note 7)FSR VDD VVREF=VDD FSR = from to VDD VREF VVREF= Internal, Gx=1, FSR = from V to VREF 2*VREF VVREF= Internal, Gx=2, FSR = from to 2 * VREFO utput VoltageSettling TimeTSETTLING 6 sNote 8 Analog Output Time Delay from power -Down ModeTdExPD sVDD=5V, Note 4, Note 9 Time delay to settle to new reference(Note 4, Note 6)TdREF 26 sFrom External to Internal Reference 44 sFrom Internal to External ReferencePower Supply Rejection PSRR -57 dBVDD=5V 10%, VREF=Internal Capacitive Load Stability CL 1000 pF RL=5k No oscillation, Note 4 Slew Rate SR V/ s Phase Margin pM 66 Degree( )CL=400pF, RL= Short Circuit Current ISC 1524mA VDD=5V, All VOUT Pins = at room Circuit Current Duration TSC_DUR Infinite hoursNote 4DC Output Impedance(Note 4)ROUT 1 Normal mode 1 k power -Down mode 1(PD1:PD0 = 0:1), VOUT to VSS 100 k power -Down mode 2(PD1:PD0 = 1:0), VOUT to VSS 500 k power -Down mode 3(PD1:PD0 = 1:1), VOUT to VSS ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Specifications.

10 Unless otherwise indicated, all parameters apply at VDD= + to , VSS=0V,RL=5k , CL= 100 pF, GX=1, TA= -40 C to +125 C. Typical values are at +25 C, VIH=VDD, VIL=VSS. ParameterSymbolMinTypicalMaxUnitsConditi onsNote 1:All digital input pins (SDA, SCL, LDAC) are tied to High , Output pins are unloaded, code = 0 x :The power -up ramp rate measures the rise of VDD over :This parameter is ensured by design and not 100% :This parameter is ensured by characterization and not 100% :Test code range: 100 - 4000 codes, VREF = VDD, VDD = :Time delay to settle to a new reference when switching from external to internal reference or vice :This parameter is indirectly tested by Offset and Gain error :Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full :This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT.


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