MICROSAR Product Information English - Vector

1 MICROSAR Classic Product Information Overview 2 Table of Contents 1 Overview .. 6 2 OS .. 7 Operating System (Os) .. 8 Multi-Core for BSW and RTE .. 8 Vector Hypervisor (veHypervisor) .. 8 Vector System Protection (veSysProt) .. 8 Vector Lean Hypervisor (veLhyp) .. 9 3 COM .. 10 Communication (Com) .. 11 COM Transformer (ComXf) .. 11 E2E Transformer (E2eXf) .. 11 I- PDU Multiplexer (IpduM) .. 11 Large Data Communication (LdCom) .. 11 Gateway Mirroring (Mirror) .. 11 Network Management (Nm) .. 11 PDU Router (PduR) .. 12 Secured Onboard Communication (SecOC) .. 12 SOME/IP Transport Protocol (SomeIpTp) .. 12 SOME/IP Transformer (SomeIpXf) .. 12 4 CAN .. 13 CAN Interface (CanIf).

2 14 CAN Network Management (CanNm).. 14 CAN Station Manager (CanSM) .. 14 CAN Transport Protocol (CanTp) .. 14 CAN Time Synchronization (CanTSyn) .. 14 CAN XCP Module (CanXcp) .. 14 Network Management for J1939 (J1939Nm) .. 14 Request Manager for J1939 (J1939Rm) .. 14 Transport Layer for J1939 (J1939Tp) .. 15 5 FR .. 16 FlexRay AUTOSAR Tranport Protocol (FrArTp) .. 17 FlexRay Interface (FrIf) .. 17 FlexRay Network Management (FrNm) .. 17 FlexRay State Manager (FrSM).. 17 FlexRay Transport Protocol (FrTp) .. 17 Time Sync Over FlexRay (FrTSyn) .. 17 FlexRay XCP Module (FrXcp) .. 17 6 LIN .. 18 LIN Interface (LinIf) .. 19 LIN State Manager (LinSM) .. 19 LIN Transport Protocol (LinTp) .. 19 7 ETH.

3 20 Vector Domain Name System Resolver (veDns) .. 21 Overview 3 Diagnostic over IP (DoIP) .. 21 Vector Diagnostic Communication over IP (veDoIPint) .. 21 Vector ECU Authentication Protocol (veEap) .. 21 Ethernet Interface (EthIf) .. 21 Ethernet State Manager (EthSM) .. 21 Time Sync Over Ethernet (EthTSyn) .. 21 XCP over Ethernet (EthXcp) .. 21 Vector Ethernet Testability Module (veEtm) .. 21 Vector Hypertext Transfer Protocol (veHttp) .. 21 Vector MACsec Key Agreement (veMka) .. 22 Service Discovery (Sd) .. 22 Socket Adaptor (SoAd) .. 22 Transmission Control Protocol/Internet Protocol (TcpIp) .. 22 UDP Network Management (UdpNm) .. 22 Vector Transport Layer Security (veTls - Client).

4 22 8 IPC .. 23 Vector Inter Process Communication (veIpc) .. 24 Vector Inter Process Communication Memory Driver (veIpcMem) .. 24 Vector Inter Process Communication Memory Interface (veIpcMemIf) .. 24 Vector Inter Process Communication SPI Interface (veIpcSpiIf) .. 24 9 CHARGE .. 25 Vector CAN Charging Communication CHAdeMO (veCanCcCdm) .. 26 Vector CAN Charging Communication GB/T 27930 (veCanCcGbt) .. 26 Vector Efficient XML Interchange (veExi) .. 26 Vector JSON Parser (veJson) .. 26 Vector Smart Charging Communication (veScc) .. 26 Vector XML Security (veXmlSecurity) .. 26 Vector XML Engine (veXmlEngine) .. 26 Vector XML Security (veXmlSecurity) .. 26 10 TSN .. 27 Vector Audio/Video Transport Protocol (veAvTp).

5 28 Stream Registration Protocol (veSrp) .. 28 11 MEM .. 29 EEPROM Abstraction (Ea) .. 30 Flash EEPROM Emulation (Fee) .. 30 Memory Abstration Interface (MemIf) .. 30 Non-Volative RAM Manager (NvM) .. 30 12 SYS .. 31 Basic Software Module Manager (BswM) .. 32 Communication Manager (ComM) .. 32 Default Error Tracer (Det) .. 32 ECU State Manager (EcuM) .. 32 Synchronized Time Base Management (StbM) .. 33 Watchdog Interface (WdgIf) .. 33 Watchdog Manager (WdgM) .. 33 Overview 4 13 DIAG .. 34 Diagnostic Communication Manager (Dcm).. 35 Diagnostic Event Manager (Dem) .. 35 Vector Diagnostic Event Synchronizer (veDes) .. 36 Vector Diagnostic Request Manager (veDrm) .. 36 Function Inhibition Manager (FiM).

6 36 Diagnostic Communication Manager for J1939 (J1939 Dcm) .. 36 14 MCAL .. 37 CAN Driver (Can) .. 38 Can (SocketCAN) .. 38 Vector Hardware Security Module (Crypto - veHsm) .. 38 Crypto Driver (Crypto Hw) .. 38 Ethernet Driver (Eth) .. 38 Ethernet Switch Driver (EthSwt) .. 38 FlexRay Driver (Fr) .. 39 Vector I2C Driver (veI2c) .. 39 LIN Driver (Lin) .. 39 Vector Multimedia Card Driver (veMmc) .. 39 Ram Test (RamTst) .. 39 15 40 CAN Transceiver Driver (CanTrcv) .. 41 External Driver (Ext) .. 41 Ethernet Transceiver Driver (EthTrcv) .. 41 FlexRay Transceiver Driver (FrTrcv).. 41 LIN Transceiver Driver (LinTrcv) .. 41 Vector Abstraction Layer for System Basis Chips (veSbc) .. 41 Vector Switch (veSwitch).

7 41 16 AMD .. 43 Debugging (Dbg) .. 44 Diagnostic Log and Trace (Dlt) .. 44 Vector Runtime Messurement (veRtm) .. 44 Vector XCP Routing (veXcpRoute) .. 44 17 IO .. 45 Vector Digital Input Output Hardware Abstraction (veDioHwAb) .. 46 18 47 Runtime Environment (Rte) .. 48 Basic Runtime Environment (Bre) .. 48 Software Cluster Connection (SwCluC) .. 49 E2E Protection Wrapper (E2ePw) .. 49 19 OTA .. 50 Vector OTA Download (veOtaDl) .. 51 20 CRYPTO .. 52 Crypto Interface (CryIf) .. 52 (Crypto - Sw) .. 52 Crypto Service Manager (Csm) .. 53 Overview 5 Intrusion Detection System Manager (IdsM) .. 53 Key Manager (KeyM) .. 53 Vector Security Modules (veSecMod) .. 53 05/2023 Please consider the environment before printing this document.

8 Overview 6 1 Overview The Complete MICROSAR Classic Stack MICROSAR Classic ensures the basic functionality of functional, AUTOSAR-compliant software in ECUs for both single-core and multi-core processors. Vector offers many OEM-specific modules and functions that go beyond the AUTOSAR standard. All modules can be configured, generated, and integrated according to the project requirements to represent a complete set of ECU software. > Sophisticated, long-term, and reliable solution from an AUTOSAR Premium Member > Entire AUTOSAR solution for and releases from a single source > Delivered as turnkey software preconfigured for specific OEM requirements > Already in production use by leading OEMs and TIER1s > Available for many hardware platforms and compilers for OS and MCAL modules > Supports many different data formats such as AUTOSAR-XML, DBC, LDF, FIBEX, CDD, ODX > Optionally delivered as source code > Detailed documentation included in the software For more Information about MICROSAR Classic, its application areas.

9 Use-cases and solutions visit OS 7 2 OS Real-Time Operating System for Microcontrollers OS is a preemptive real time multitasking operating system with optimized features for usage on microcontrollers, fully compliant with the AUTOSAR OS specification (former OSEK/VDX-OS) and includes useful functions like time monitoring and memory protection. Protected by the System Memory Protection Unit, different partitions can be operated free of memory access interference, allowing partitions with different ASIL to run in parallel. The Vector Lean Hypervisor (veLhyp) ensures safe startup of multiple operating system partitions in a multi-core processor or SoC and initializes the system MPU. > Small, robust, quick, and resource-economizing operating system and with short boot times > Graphic configuration tool for easy configuration > Timing resolutions below 1ms without increasing interrupt load (High-Resolution Timer) > Possible resolutions in microsecond range (hardware dependent) > Available for many 16-, 32- and 64-bit microcontrollers and as multi-core operating system (AUTOSAR 4 and 3) > Safe start-up of multiple operating system partitions > Implementation according to ISO 26262 ASIL D > Freely selectable master core OS 8 Operating System (Os) The OS module is an extended OSEK operating system for AUTOSAR ECUs (also available as GuestOS Linux and QNX)

10 Which supports multi-core microcontrollers and can be run in safety-related environments. The variations are divided into Scalability Classes (SC), offering Schedule Tables, Timing Protection (time synchronization to measure and monitor tasks and interrupt service routines) and Memory Protection (mechanisms for easier and more reliable integration of applications). > SC1: Schedule Tables > SC2: Schedule Tables and Timing Protection > SC3: Schedule Tables and Memory Protection > SC4: Schedule Tables, Timing Protection and Memory Protection Add-Ons > Multi-Core (symmetric): For multi-core systems with a same set of commands > Multi-Core (asymmetric): For multi-core system with a different set of commands. Multi-Core for BSW and RTE Allows to distribute the application specific workload to different cores.