ML145146 4–Bit Data Bus Input PLL Frequency …

1 ML145146 . 4 bit data bus input PLL. Frequency Synthesizer INTERFACES WITH DUAL MODULUS PRESCALERS. Legacy Device: Motorola MC145146-2. The ML145146 is programmed by a 4 bit Input , with strobe and address lines. The device features consist of a P DIP 20 = RP. PLASTIC DIP. reference oscillator, 12 bit programmable reference CASE 738. 20. divider, digital phase detector, 10 bit programmable 1. divide by N counter, 7 bit divide by A counter, and the necessary latch circuitry for accepting the 4 bit Input data . SOG 20 W = -6P. 20 SOG PACKAGE. Operating Temperature Range: TA 40 to +85 C CASE 751D. Low Power Consumption Through the Use of 1. CMOS Technology CROSS REFERENCE/ORDERING INFORMATION. to V Supply Range PACKAGE MOTOROLA LANSDALE. P DIP 20 MC145146P2 ML145146RP. Programmable Reference Divider for Values Between SOG 20W MC145146DW2 ML145146 -6P.

2 3 and 4095. Note: Lansdale lead free (Pb) product, as it Dual Modulus 4 Bit data Bus Programming becomes available, will be identified by a part N Range = 3 to 1023, A Range= 0 to 127 number prefix change from ML to MLE. Linearized Digital Phase Detector Enhances Transfer Function Linearity Two Error Signal Options: PIN ASSIGNMENT. Single Ended (Three State). D1 1 20 D2. Double Ended D0 2 19 D3. fin 3 18 fR. VSS 4 17 R. BLOCK DIAGRAM. PDout 5 16 V. VDD 6 15 fV. OSCin 12 BIT R COUNTER fR. OSCin 7 14 MC. OSCout OSCout 8 13 LD. L5 L6 L7 LOCK. LD. DETECT A0 9 12 ST. D0. D1 A1 10 11 A2. D2 PHASE. D3 DETECTOR A PDout A2 LATCH. A1 CONTROL LATCHES. fV. A0 CIRCUITRY. ST. PHASE V. L2 L3 L4 L0 L1. DETECTOR B R. fin 10 BIT N COUNTER 7 BIT A COUNTER. CONTROL LOGIC MODULUS CONTROL (MC). Page 1 of 12 Issue 0. ML145146 LANSDALE Semiconductor, Inc.

3 Page 2 of 12 Issue 0. ML145146 LANSDALE Semiconductor, Inc. Page 3 of 12 Issue 0. ML145146 LANSDALE Semiconductor, Inc. Page 4 of 12 Issue 0. ML145146 LANSDALE Semiconductor, Inc. Page 5 of 12 Issue 0. ML145146 LANSDALE Semiconductor, Inc. PIN DESCRIPTIONS LD. Lock Detector (Pin 13). Input PINS. High level when loop is locked (fR, fV of same phase and D0 - D3 Frequency ). Pulses low when loop is out of lock. data Inputs (Pins 2, 1, 20, 19). MC. Information at these inputs is transferred to the internal Modulus Control (Pin 14). latches when the ST Input is in the high state. D3 (Pin 19) is the most significant bit. Signal generated by the on chip control logic circuitry for controlling an external dual modulus prescaler. The modulus f in control level is low at beginning of a count cycle and remains Frequency Input (Pin 3) low until the A counter has counted down from its pro- Input to N portion of synthesizer f in is typically derived grammed value.

4 At this time, modulus control goes high and from loop VCO and is AC coupled into Pin 3. For larger remains high until the N counter has counted the rest of the amplitude signals (standard CMOS logic levels) DC coupling way down from its programmed value (N A additional count- may be used. er since both N and A are counting down during the first portion of the cycle). Modulus control is then set back low, the OSCin/OSCout counters preset to their respective programmed values, and the Reference Oscillator Input /Output (Pins 7 and 8) above sequence repeated. This provides for a total programma- ble divide value (NT) = N P A where P and P 1 represent These pins form an on chip reference oscillator when con- the dual modulus prescaler divide values respectively for high nected to terminals of an external parallel resonant crystal.

5 And low modulus control levels. N the number programmed Frequency setting capacitors of appropriate value must be con- into the N counter and A the number programmed into the nected from OSCin to ground and OSCout to ground. OSCin A counter. may also serve as Input for an externally generated reference signal. This signal is typically AC coupled to OSCin, but for fV. larger amplitude signals (standard CMOS logic levels) DC N Counter Output (Pin 15). coupling may also be used. In the external reference mode, no This pin is the output of the N counter that is internallly connection is required to OSCout. connected to the phase detector Input . With this output avail- A0 - A2 able, the N counter can be used independently. Address Inputs (Pins 9, 10, 11) V, R. A0, A1 and A2 are used to define which latch receives the Phase Detector Outpiuts (Pins 16 adn 17).

6 Information on the data Input lines. The addresses refer to the These phase detector outputs can be combined externally for following latches. a loop error signal. A single ended output is also available for this purpose (see PDout). If Frequency fV is greater than fR or if the phase of fV is A2 A1 A0 Selected Function D0 D1 D2 D3. leading, then error information is provided by V pulsing low 0 0 0 Latch 0 A Bits 0 1 2 3 R remains essentially high. 0 0 1 Latch 1 A Bits 4 5 6 If the Frequency fV is less than fR or if the phase of fV is 0 1 0 Latch 2 N Bits 0 1 2 3 lagging, then error information is provided by R pulsing low 0 1 1 Latch 3 N Bits 4 5 5 7 V remains essentially high. 1 0 0 Latch 4 N Bits 8 9 If the Frequency of fV = fR and both are in phase, then both 1 0 1 Latch 5 Reference Bits 0 1 2 3. V and R remain high except for a small minimum time peri- 1 1 0 Latch 6 Reference Bits 4 5 6 7.

7 Od when both pulse low in phase. 1 1 1 Latch 7 Reference Bits 8 9 10 11 fR. R Counter Output (Pin 18). ST. Strobe Transfer (Pin 12) This is the output of the R counter that is internally con- nected to the phase detector Input . With this output available, The rising edge of strobe transfers data into the addressed the R counter can be used independently. latch. The falling edge of strobe latches data into the latch. This pin should normally be held low to avoid loading latches POWER SUPPLY PINS. with invalid data . VSS. OUTPUT PINS Ground (Pin 4). PDout Circuit Ground Single ended Phase Detector Output (Pin 5) VDD. Three state output of phase detector for use as loop error Positive Power Supply (Pin 6). signal. The positive supply voltage may range from to V. Frequency fV>fR or fV Leading: Negative Pulses with respect to VSS.

8 Frequency fV<fR or fV Lagging: Negative Pulses Frequency fV=fR and Phase Coincidence: High Impedance State Page 6 of 12 Issue 0. ML145146 LANSDALE Semiconductor, Inc. Page 7 of 12 Issue 0. ML145146 LANSDALE Semiconductor, Inc. DESIGN CONSIDERATIONS The oscillator can be trimmed on Frequency by making a portion or all of C1 variable. The crystal and associated com- CRYSTAL OSCILLATOR CONSIDERATIONS ponents must be located as close as possible to the OSCin and The following options may be considered to provide a refer- OSCout pins to minimize distortion, stray capacitance, stray ence Frequency to Motorola's CMOS Frequency synthesizers. inductance, and startup stabilization time. In some cases, stray The most desirable is discussed first. capacitance should be added to the value for Cin and Cout. Power is dissipated in the effective series resistance of the Use of a Hybrid Crystal Oscillator crystal, Re.

9 In Figure 10 The drive level specified by the crys- Commercially available temperature compensated crystal tal manufacturer is the maximum stress that a crystal can with- oscillators (TCXOs) or crystal controlled data clock oscilla- stand without damaging or excessive shift in Frequency . R1 in tors provide very stable reference frequencies. An oscillator Figure 8 limits the drive level. The use of R1 may not be nec- capable of sinking and sourcing 50 A at CMOS logic levels essary in some cases ( R1 = 0 ohms). may be direct or DC coupled to OSCin. In general, the highest To verify that the maximum DC supply voltage does not Frequency capability is obtained utilizing a direct coupled overdrive the crystal, monitor the output Frequency as a func- square wave having a rail to rail (VDD to VSS) voltage tion of voltage at OSCout.

10 (care should be taken to minimize swing. If the oscillator does not have CMOS logic levels on the loading.) the Frequency should increase very slightly as the dc outputs, capacitive or AC coupling of OSCin may be used. supply voltage is increased. An overdriven crystal will decrease OSCout, an unbuffered output, should be left floating. in Frequency or become unstable with an increase in supply For additional information about TCXOs and data clock voltage. The operating supply voltage must be reduced or R1. oscillators, please consult the latest version of the eem must be increased in value if the overdrive condition exists. Electronic Engineers Master Catalog, the Gold Book, or simi- The user should note that the oscillator start up time is propor- lar publications. tional to the value of R1. Design an Off Chip Reference Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have developed The user may design and off chip crystal oscillator using expertise in CMOS oscillator design with crystals.