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Modeling of Integrated RF Passive Devices - …

Modeling of Integrated RF Passive DevicesSharad Kapur and David E. LongCustom Integrated Circuits Conference, Introduction and motivation Three topics EM simulation using Integral methods Modeling layout dependent effects circuit models and component synthesis Experiments ConclusionsOutline2 Applications Applications Mobile Wireless (WiFi, WiMax) Wired (Ethernet) Storage (Hard disks) Passive components found these Devices A decade ago inductors, MIM capactors Now a whole range of components and Devices are being used3 Tech trends Thick metals 3um to 8um copper High-resistivity substrates 10 -cm to 1000 -cm Fine feature sizes m width at 65nm Many metal layers High density MOM capacitors instead of MIM (2fF vs 4fF)4 IC processes offer tight tolerances Low variability Chip real estate is expensive Integration offers big cost savings No extra packaging Much tighter tolerances and better yield When a device can be built with reasonable quality compared to an off-chip or an LTCC structure it will be Integrated Devices that used be considered exotic are now routinely used IC processes5 P

Modeling of Integrated RF Passive Devices Sharad Kapur and David E. Long Custom Integrated Circuits Conference, 2010 www.integrandsoftware.com Introduction …

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1 Modeling of Integrated RF Passive DevicesSharad Kapur and David E. LongCustom Integrated Circuits Conference, Introduction and motivation Three topics EM simulation using Integral methods Modeling layout dependent effects circuit models and component synthesis Experiments ConclusionsOutline2 Applications Applications Mobile Wireless (WiFi, WiMax) Wired (Ethernet) Storage (Hard disks) Passive components found these Devices A decade ago inductors, MIM capactors Now a whole range of components and Devices are being used3 Tech trends Thick metals 3um to 8um copper High-resistivity substrates 10 -cm to 1000 -cm Fine feature sizes m width at 65nm Many metal layers High density MOM capacitors instead of MIM (2fF vs 4fF)4 IC processes offer tight tolerances Low variability Chip real estate is expensive Integration offers big cost savings No extra packaging Much tighter tolerances and better yield When a device can be built with reasonable quality compared to an off-chip or an LTCC structure it will be Integrated Devices that used be considered exotic are now routinely used IC processes5 Passive components6inductorind + shieldMOM capTransformerFull circuits7 Full circuit1 Diplexer2 VCO3: inductors + interconnect+ capacitor bank1.

2 SiGe Semiconductor on IBM BiCMOS2. STATS ChipPAC IPD technology3. Wipro on TSMC 90nm Increased prevalence of passives has made fast and accurate Modeling critical Two aspects to (EM) simulation to evaluate candidate designs (and possible refinement) EM simulation results that can be used in higher level simulators (like Spice).Modeling8 Two broad categories for solving Maxwell s formulations Finite-difference, Finite element (FEM), Formulations Method-of-Moments, Boundary element (BEM), Integral equation solvers EM simulation9 Differential vs IntegralDiff formulations Flexible Imposes no constraint on shape of metals, dielectric regions Need to enforce Maxwell s equations everywhere surrounding the object Leads to largesparse matrix solveIntegral formulations Planar dielectrics, conductors Need to enforce Maxwell s equations only on conductors (Green s theorem)

3 Leads to smaller dense matrix to solve Many techniques developed recently For IC passives this approach is the best103D Integral Formulation in EMX EMXis a 3D EM simulator 3D volume integral formulation (time harmonic) Unknowns (charge and currents) Surface charges Volume currents 3D: Current vectors can be in x-y-z directions 11 Matrix formulation Suppose that N elements in the mesh Conventional approach O(N3) time and O(N2) memory Cost is prohibitive Double the size of the problem 8X time12(continuous form)BAx (A is a dense matrix) Iterative methods were developed in the numerical analysis community (GMRES, Yale, 1986) Matrix vector products instead of matrix inversion This reduced the time to O(N2)Innovations in numerical methods (GMRES)13bAx }.

4 ,,,{2bAbAAbbKnn The Fast Multipole Method was developed in 1987 Developed N-body problem Applied to capacitance byWhite at MIT for FastCap, Fast Henry, (1990s). Applied to field solution IES3,Bell Labs, Kapur and Long, (1990s) These sorts of problems can be solved in linear time (with a large constant) All recent effort is decreasing this costInnovations in numerical methods (FMM)14bAx Exploiting regularity15 Mesh generation was regarded as an orthogonal sub problem (typically unstructured Delaunytriangulation) Layout has a lot of structure This structure can be imposed on the mesh Identical interactions are repeated all overAdaptive frequency sweep An adaptive frequency sweep Reduced order model using Krylov subspace methods Methods developed in the 00s (Bell Labs, MIT, CMU, Intel)}

5 The reduced order model from a small set of EM solutions Only few simulations need to be done16 Time and Memory scaling Single frequency simulation (including iterative solve) Compare speed and memory for 1, 2, 4, 8, .., 64 inductors171 inductor64 inductorsExamples: Spiral Inductor183D meshCurrentCourtesy: TSMC. 65nm RFCMOS, 9LM thick metal technology. Published at RFIC 2009 Including Pattern-Dependent Effects in Electromagnetic Simulations of On-Chip Passive Components , Integrand and TSMCS tandard high Q spiral inductor used in lots of circuits. Thick copper and large Inductor193D meshCurrentCourtesy: TSMC. 65nm RFCMOS, 9LM thick metal technology. Published at RFIC 2009 Including Pattern-Dependent Effects in Electromagnetic Simulations of On-Chip Passive Components , Integrand and TSMCS mall stacked inductor.

6 High inductance low Q (used in Chokes). Upto 20-30nH in small areaMOM (finger)Capacitor203D mesh of CapCourtesy: TSMC. 65nm RFCMOS, 9LM thick metal technology. Published at RFIC 2009 Including Pattern-Dependent Effects in Electromagnetic Simulations of On-Chip Passive Components , Integrand and TSMCHigh-density MOM caps (at 40nm can be 4fF/square micron). Important to parasitic inductance to get 213D meshCurrentCourtesy: UMC. 90nm RFCMOS, 8LM thick metal technology. Published at CICC 2007 Synthesis of Optimal On-Chip Baluns , Integrand and UMCUsed as a part of matching network. Can get reanonably high coupling k values of in a standard thick metal CMOS processBalun (with MiM caps)223D meshCurrentCourtesy: UMC. 90nm RFCMOS, 8LM thick metal technology.

7 Published at CICC 2007 Synthesis of Optimal On-Chip Baluns , Integrand and UMCA balunis a Passive component that transforms power from a BALanced to an UNbalanced port. FOM is usually insertion loss. 1dB insertion loss and is very competitive with off chip Diplexer (with Thru Silicon Vias)233D meshCurrentCourtesy: SiGe Semiconductor. IBM BiCMOS 5 PAE. Diplexer has a high-band and low band filter in the same circuit . Used in chips which operate in multiple bands. Fully Passive circuit with inductors, resistors, capacitors, TSVs. Need to model all effects and Diplexer243D meshCurrentCourtesy: STATSChipPAC, IPD technology (8um Cu on high resistivity Si substrate)Built on a lossless substrate so coupling is very strong between of design is to create inductors with EM simulation.

8 Tune with caps. Resimulate and re design. Simulation time of about 1 hour for full VCO253D mesh (inductor+ capacitor bank)Courtesy: Wipro, TSMC90nm, 1P5 MHigh-frequency VCO. Inductor and 66 MiM capacitor bank. Inductor is small so coupling between inductor and interconnect must be considered. Block by block model fails to predict VCO behavior. Multi-threaded EMX is 2-3X faster for small examples and 5-7X faster for larger examples on an 8 CPU machine. The memory for the multi-threaded version goes up at a slower rate than the Summary26 In IC processes the width, thickness and resistance of wires vary depending on the width and spacing of the surrounding wires These effects are called pattern dependent effects Width and spacing dependence in the process description EMX modifies the layout to mimic the fabrication process Leads to improved simulation and Modeling accuracyLayout dependent effects 27 Fabricated metal width varies as a function of width and spacing of wires Physical width vs drawn width as a function of width and spacing Width can vary by 50%from drawn widthPattern dependent effects28 Sheet resistance varies as a function of width and spacing of wires Sheet resistance as a function of width and spacing Sheet resistance can vary by 200%Pattern dependent effects29 EMX

9 Automatically modifies IC layout to mimic fabrication effects When you have uniformly spaced wires width and spacing have intuitive meanings Need to come up with a definition of width and spacing for general layout. What happens when you have non-uniform layout?Mimic fabrication effects30 Fabricated width is different from drawn width according to rules provided by foundry by a bias amount Shaded regions represent original drawn geometry Lines represents modified grown geometry based on local width and spacingModifying layout 31 EMX simulation of MOM capacitorsThe iRCX width-and-spacing dependence is more critical for structures that are not at minimum dimensions. The accuracy of EMX using iRCX is increased since the fabrication process is mimicked more simulation of Stacked inductors Once you have S-parameters from simulation Can use Harmonic Balance and do higher-level simulations in the frequency domain For transient analysis need time domain representation Best to have a true Spice Model (RLCK) with positive values, etc.

10 The way it can be done is to fit to a prescribed topology using certain constraints. Often scalable models are required which are parameterized models based on layout parameterized by an automated layout EM simulations over the design a scalable an optimizer to determine the optimal layout and tuning capacitor values based on designer inputsOptimal balun an automated layout EM simulations over the design a scalable an optimizer to determine the optimal layout and tuning capacitor values based on designer inputsOptimal balun syntheis36 Layout generation Parameterized layout generator for transformers The design space turns ratio number of turns width outer diameter Create about 1000 transformer layouts37EM solution38 Simulate the layout from DC to Mesh of Baluncurrent flow The topology


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