MSP430x1xx Family User's Guide (Rev. F) - TI.com

1 2006 Mixed Signal ProductsUser s GuideSLAU049F1 SLAZ671A April 2015 Revised December 2016 Submit Documentation FeedbackCopyright 2015 2016, texas instruments IncorporatedCorrections to MSP430x1xx Family User's Guide (SLAU049)Manual Update SheetSLAZ671A April 2015 Revised December 2016 Corrections to MSP430x1xx Family User's Guide (SLAU049)Document Being Updated: MSP430x1xx Family User's GuideLiterature Number Being Updated: SLAU049 FPageChange or Add146 (5-20) InFCTL3, Flash Memory Control Register FCTL3, the BUSY bit is shown as "r(w) 0". Thecorrect value is "r 0".562 (19-12) The following note should be added at the end of theIrDA Decodingsection:NOTE: Reliable reception of IrDA signalsTo receive incoming IrDA signals reliably, make sure that at least one of thefollowing procedures are implemented: Enable the digital filter stage with UCIRRXFE = 1.

2 Use a parity bit to detect corrupted bytes. Check the correctness of received data frames using a checksum orCRC. With parity or CRC checks, use a protocol that acknowledges receiveddata frame and resends data if the sender does not receive anacknowledgment. Related Documentation From texas Instrumentsiii Preface About This ManualThis manual discusses modules and peripherals of the MSP430x1xx Family ofdevices. Each discussion presents the module or peripheral in a generalsense. Not all features and functions of all modules or peripherals are presenton all devices. In addition, modules or peripherals may differ in their exactimplementation between device families, or may not be fully implemented onan individual device or device functions, internal signal connections and operational paramenters differfrom device-to-device.

3 The user should consult the device-specific datasheetfor these Documentation From texas InstrumentsFor related documentation see the web site WarningThis equipment is intended for use in a laboratory test environment only. It gen-erates, uses, and can radiate radio frequency energy and has not been testedfor compliance with the limits of computing devices pursuant to subpart J ofpart 15 of FCC rules, which are designed to provide reasonable protectionagainst radio frequency interference. Operation of this equipment in other en-vironments may cause interference with radio communications, in which casethe user at his own expense will be required to take whatever measures maybe required to correct this ConventionsProgram examples, are shown in a special ClockSee Basic Clock ModuleADCA nalog-to-Digital ConverterBORB rown-Out ResetSee System Resets, Interrupts.

4 And Operating ModesBSLB ootstrap LoaderSee for application reportsCPUC entral Processing UnitSee RISC 16-Bit CPUDACD igital-to-Analog ConverterDCOD igitally Controlled Oscillator See Basic Clock ModuledstDestinationSee RISC 16-Bit CPUFLLF requency Locked LoopSee FLL+ in MSP430x4xx Family user s GuideGIEG eneral Interrupt EnableSee System Resets Interrupts and Operating ModesINT(N/2) Integer portion of N/2I/OInput/OutputSee Digital I/OISRI nterrupt Service RoutineLSBL east-Significant BitLSDL east-Significant DigitLPMLow-Power ModeSee System Resets Interrupts and Operating ModesMABM emory Address BusMCLKM aster ClockSee Basic Clock ModuleMDBM emory Data BusMSBMost-Significant BitMSDMost-Significant DigitNMI(Non)

5 -Maskable InterruptSee System Resets Interrupts and Operating ModesPCProgram CounterSee RISC 16-Bit CPUPORP ower-On ResetSee System Resets Interrupts and Operating ModesPUCP ower-Up ClearSee System Resets Interrupts and Operating ModesRAMR andom Access MemorySCGS ystem Clock GeneratorSee System Resets Interrupts and Operating ModesSFRS pecial Function RegisterSMCLKSub-System Master ClockSee Basic Clock ModuleSPStack PointerSee RISC 16-Bit CPUSRS tatus RegisterSee RISC 16-Bit CPUsrcSourceSee RISC 16-Bit CPUTOSTop-of-StackSee RISC 16-Bit CPUWDTW atchdog TimerSee Watchdog Timer Register Bit Conventionsv Register Bit ConventionsEach register is shown with a key indicating the accessibility of the eachindividual bit, and the initial condition:Register Bit Accessibility and Initial ConditionKeyBit AccessibilityrwRead/writerRead onlyr0 Read as 0r1 Read as 1wWrite onlyw0 Write as 0w1 Write as 1(w)No register bit implemented; writing a 1 results in a register bit is always read as by hardwareh1 Set by hardware 0, 1 Condition after PUC (0), (1)Condition after PORvi Contentsvii 1 Introduction1-1.

6 Clock System1-2.. Emulation1-3.. Space1-4.. Modules1-5.. Function Registers (SFRs)1-5.. Organization1-5.. 2 System Resets, Interrupts, and Operating Modes2-1.. Reset and Initialization2-2.. Reset (POR)2-3.. Reset (BOR)2-4.. Initial Conditions After System Reset2-5.. (Non)-Maskable Interrupts (NMI)2-7.. Interrupts2-10.. Processing2-11.. Vectors2-13.. Modes2-14.. and Exiting Low-Power Modes2-16.. for Low-Power Applications2-17.. of Unused Pins2-17.. Contentsviii3 RISC 16-Bit CPU3-1.. Introduction 3-2.. Registers3-4.. Counter (PC)3-4.. Pointer (SP)3-5.

7 Register (SR)3-6.. Generator Registers CG1 and CG23-7.. Purpose Registers R4 - R153-8.. Modes3-9.. Mode3-10.. Mode3-11.. Mode3-12.. Mode3-13.. Register Mode3-14.. Autoincrement Mode3-15.. Mode3-16.. Set3-17.. (Format I) Instructions3-18.. (Format II) Instructions3-19.. Cycles and Lengths3-72.. Set Description3-74.. 4 Basic Clock Module4-1.. Clock Module Introduction4-2.. Clock Module Operation4-4.. Clock Module Features for Low-Power Applications4-4.. Oscillator4-5.. Oscillator4-6.. Oscillator (DCO)4-6.. Modulator4-9.. Clock Module Fail-Safe Operation4-10.

8 Of Clock Signals4-13.. Clock Module Registers 4-14.. 5 Flash Memory Controller5-1.. Memory Introduction5-2.. Memory Segmentation5-3.. Memory Operation5-4.. Memory Timing Generator5-4.. Flash Memory5-5.. Flash Memory5-8.. Memory Access During Write or Erase5-14.. a Write or Erase Cycle5-15.. and Accessing the Flash Memory Controller5-15.. Memory Controller Interrupts5-15.. Flash Memory Devices5-15.. Memory Registers5-17.. Contentsix 6 Supply Voltage Supervisor6-1.. Introduction6-2.. Operation6-4.. the SVS6-4.. Comparator Operation6-4.. the VLDx Bits6-5.

9 Operating Range6-6.. Registers6-7.. 7 Hardware Multiplier7-1.. Multiplier Introduction7-2.. Multiplier Operation7-3.. Registers7-3.. Registers7-4.. Examples7-5.. Addressing of RESLO7-6.. Interrupts7-6.. Multiplier Registers7-7.. 8 DMA Controller8-1.. Introduction8-2.. Operation8-4.. Addressing Modes8-4.. Transfer Modes8-5.. DMA Transfers8-12.. DMA Transfers8-14.. Channel Priorities8-14.. Transfer Cycle Time8-15.. DMA with System Interrupts8-16.. Controller Interrupts8-16.. the I2C Module with the DMA Controller8-17.. Using ADC12 with the DMA Controller8-17.

10 Using DAC12 With the DMA Controller8-17.. Registers8-18.. 9 Digital I/O9-1.. I/O Introduction9-2.. I/O Operation 9-3.. Register PnIN9-3.. Registers PnOUT9-3.. Registers PnDIR9-3.. Select Registers PnSEL9-4.. and P2 Interrupts9-5.. Unused Port Pins9-6.. I/O Registers 9-7.. Contentsx10 Watchdog Timer10-1.. Watchdog Timer Introduction10-2.. Watchdog Timer Operation10-4.. Watchdog Timer Counter10-4.. Watchdog Mode10-4.. Interval Timer Mode10-4.. Watchdog Timer Interrupts10-5.. Operation in Low-Power Modes10-6.. Software Examples10-6.