MT9P031 - 1/2.5-Inch 5 Mp CMOS Digital Image Sensor

1 DATA Semiconductor Components Industries, LLC, 2006 August, 2021 Rev. 111 Publication Order Number: MT9P031 /D1 5 Mp CMOSD igital Image SensorMT9P031 General DescriptionThe onsemi MT9P031 is a 1 inch CMOS active pixel digitalimage Sensor with an active imaging pixel array of 2592 H x 1944 V. Itincorporates sophisticated camera functions on chip such aswindowing, column and row skip mode, and snapshot mode. It isprogrammable through a simple two wire serial 5 Mp CMOS Image Sensor features onsemi s breakthroughlow noise CMOS imaging technology that achieves CCD imagequality (based on signal to noise ratio and low light sensitivity )while maintaining the inherent size, cost, and integration advantagesof 1. KEY PERFORMANCE PARAMETERSP arameterValueOptical Format1 (4.)

2 3)Active Imager mm (H) x mm (V) mm DiagonalActive Pixels2592 H x 1944 VPixel x mColor Filter ArrayRGB Bayer PatternShutter TypeGlobal Reset Release (GRR),Snapshot OnlyElectronic Rolling Shutter (ERS)Maximum Data Rate / Pixel Clock96 Mp/s at 96 MHz ( V I/O)48 Mp/s at 48 MHz ( V I/O)Frame RateFull ResolutionProgrammable up to 14 fpsHDTV (640 x 480,with binning)Programmable up to 53 fpsADC Resolution12-bit, V/lux-sec (550 nm)Pixel Dynamic dBSupply V ( V Nominal) V ( V Nominal)Power Consumption381 mW at 14 fps Full ResolutionOperating Temperature 30 C to +70 CPackaging48-pin iLCC, DieSee detailed ordering and shipping information on page 2 ofthis data INFORMATIONILCC48 10x10 CASE 847 AAApplications High Resolution Network Cameras Wide FOV Cameras 720 P 60 fps Cameras Dome Cameras with Electronic Pan, Tile, and Zoom Hybrid Video Cameras with HighResolution Stills Detailed Feature Extraction for SmartCamerasFeatures High Frame Rate Superior Low-light Performance Low Dark Current Global Reset Release, which Starts theExposure of All Rows Simultaneously Bulb Exposure Mode.

3 For ArbitraryExposure Times Snapshot Mode to Take Frames on Demand Horizontal and Vertical Mirror Image Column and row skip modes to reduceimage size without reducing field of view(FOV) Column and Row Binning Modes toImprove Image Quality when Resizing Simple Two-wire Serial Interface Programmable Controls: Gain, Frame Rate,Frame Size, Exposure Automatic Black Level Calibration On-chip Phase-Locked Loop (PLL) InformationTable 2. AVAILABLE PART NUMBERS Part NumberProduct DescriptionOrderable Product Attribute DescriptionMT9P031D00 STCC18BC1 2005 MP 1/3 CISDie Sales, 200mm ThicknessMT9P031D00 STMC18BC1 2005 MP 1/3 CISDie Sales, 200mm ThicknessMT9P031I12 STC DP5 MP 1/3 CISDry Pack with Protective FilmMT9P031I12 STC DR5 MP 1/3 CISDry Pack without Protective FilmMT9P031I12 STC DR15 MP 1/3 CISDry Pack Single Tray without Protective FilmMT9P031I12 STC TP5 MP 1/3 CISTape & Reel with Protective FilmMT9P031I12 STM DP5 MP 1/3 CISDry Pack with Protective FilmMT9P031I12 STM DP15 MP 1/3 CISDry Pack Single Tray with Protective FilmMT9P031I12 STM DR5 MP 1/3 CISDry Pack without Protective FilmMT9P031I12 STM DR15 MP 1/3 CISDry Pack Single Tray without Protective FilmDescriptionThe MT9P031 Sensor can be operated in its default modeor programmed by the user for frame size, exposure, gainsetting, and other parameters.

4 The default mode outputs afull resolution Image at 14 frames per second (fps).An on chip analog to Digital converter (ADC) provides12 bits per pixel. FRAME_VALID (FV) and LINE_VALID(LV) signals are output on dedicated pins, along with a pixelclock that is synchronous with valid MT9P031produces extraordinarily clear, sharpdigital pictures, and its ability to capture both continuousvideo and single frames makes it the perfect choice for awide range of consumer and industrial applications,including cell phones, Digital still cameras, Digital videocameras, and PC OverviewThe MT9P031 is a progressive scan Sensor that generatesa stream of pixel data at a constant frame rate. It uses anon chip, phase locked loop (PLL) to generate all internalclocks from a single master input clock running between6 and 27 MHz.

5 The maximum pixel rate is 96 Mp/s,corresponding to a clock rate of 96 MHz. Figure 1 illustratesa block diagram of the 1. Block DiagramPixel Array2752H x 2004 VSCLKSDATASADDRPIXCLKDOUT[11:0]LVFVSTROB EA nalog Signal ChainData PathTRIGGEREXTCLKRESET_BARSTANDBY_BAROEA rray ControlOutputSerialInterfaceUser interaction with the Sensor is through the two wireserial bus, which communicates with the array control,analog signal chain, and Digital signal chain. The core of thesensor is a 5 Mp active pixel array. The timing and controlcircuitry sequences through the rows of the array, resettingand then reading each row in turn. In the time intervalbetween resetting a row and reading that row, the pixels inthe row integrate incident light. The exposure is controlledby varying the time interval between reset and readout.

6 Oncea row has been read, the data from the columns is sequencedthrough an analog signal chain (providing offset correctionand gain), and then through an ADC. The output from theADC is a 12 bit value for each pixel in the array. The ADCoutput passes through a Digital processing signal chain(which provides further data path corrections and appliesdigital gain). The pixel data are output at a rate of up to96 Mp/s, in addition to frame and line 2. Typical Configuration (Connection)DOUT[11:0] 1 VDD_IO2,3 VDDVDD2,31 FRSVDDGND3 VDD_PLLVAA_PIXVAAVAA2, NOTE:1. A resistor value of k is recommended, but may be greater for slower two-wire All power supplies should be adequately All DGND pins must be tied together, as must all AGND pins, all VDD_IO pins, and all VDD 3.

7 48-Pin iLCC 10 x 10 Package Pinout Diagram (Top View)12345644431920212223242526272829307 8910111213141516424140393837363534333231 FRAME_VALIDLINE_VALIDSTROBEDGNDVDD_IOVDD SADDRSTANDBY_BARTRIGGERRESET_BAROENCDOUT 8 DOUT7 DOUT6 VDD_IODOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 PIXCLKEXTCLKNCTESTTESTAGNDVAAVAAVDD_PLLD GNDNCNCNCNCRSVDSDATASCLKTESTAGND 3. PIN DESCRIPTIONNameTypeDescriptionRESET_BARI nputWhen LOW, the MT9P031 asynchronously resets. When driven HIGH, it resumes normal operation with all configuration registers set to factory input clock. Pull to VDD_IO with a k HIGH, the PIXCLK, DOUT, FV, LV, and STROBE outputs enter a driven LOW, normal operation When LOW, the chip enters a low-power standby mode. It resumesnormal operation when the pin is driven trigger.

8 Used to trigger one frame of output in snapshot modes, and to indicate the end of exposure in bulb exposure address. When HIGH, the MT9P031 responds to device ID (BA)H. When LOW, it responds to serial device ID (90) data. Pull to VDD_IO with a k clock. The DOUT, FV, LV, and STROBE outputs should be captured on thefalling edge of this [11:0]OutputPixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of eachpixel, to be captured on the falling edge of valid. Driven HIGH during active pixels and horizontal blanking of eachframe and LOW during vertical valid. Driven HIGH with active pixels of each line and LOW during blank-ing strobe. Driven HIGH when all pixels are exposing in supply voltage. Nominally supply voltage. Nominally or supply voltage.

9 Nominally supply voltage. Nominally V, connected externally to supply voltage. Nominally V, connected externally to Tie to AGND for normal device operation (factory use only).RSVD Tie to DGND for normal device operation (factory use only).NC No Data FormatPixel Array StructureThe MT9P031 pixel array consists of a 2752 column by2004 row matrix of pixels addressed by column and address (column 0, row 0) represents the upper rightcorner of the entire array, looking at the Sensor , as shown inFigure array consists of a 2592 column by 1944 row activeregion in the center representing the default output Image ,surrounded by a boundary region (also active), surroundedby a border of dark pixels (see Table 4 and Table 5). Theboundary region can be used to avoid edge effects whendoing color processing to achieve a 2592 x 1944 resultimage, while the optically black column and rows can beused to monitor the black are output in a Bayer pattern format consisting offour colors GreenR, GreenB, Red, and Blue (Gr, Gb, R,B) representing three filter colors.

10 When no mirror modesare enabled, the first row output alternates between Gr andR pixels, and the second row output alternates between Band Gb pixels. The Gr and Gb pixels have the same colorfilter, but they are treated as separate colors by the data pathand analog signal 4. PIXEL TYPE BY COLUMNC olumnPixel Type0 9 Dark (10)10 15 Active boundary (6)16 2607 Active Image (2592)2608 2617 Active boundary (10)2618 2751 Dark (134)Table 5. PIXEL TYPE BY ROWC olumnPixel Type0 49 Dark (50)50 53 Active boundary (4)54 1997 Active Image (1944)1998 2001 Active boundary (3)2002 2003 Dark (2)Figure 4. Pixel Array Description(2751, 2003)10 black columns2 black rows50 black rows(0,0)134 black columnsActive Image2592 x 1944active pixels4 (16,54)6104 Figure 5. Pixel Color Pattern Detail (Top Right Corner)First clearpixel (10,50)black pixelscolumn readout Readout OrderBy convention, the Sensor core pixel array is shown withpixel (0,0) in the top right corner (see Figure 4).