Non-Volatile Memory Host Controller Interface - NVM Express

1 NVM Express NVM Express . Revision January 23, 2013. Please send comments to Amber Huffman Incorporates ECNs 001 033. 1. NVM Express NVM Express revision specification available for download at NVM Express revision ratified on March 1, 2011. NVM Express revision incorporates ECNs 001 033. LEGAL NOTICE: Copyright 2007 - 2014 NVM Express , Inc. ALL RIGHTS RESERVED. This NVM Express revision specification is proprietary to the NVM Express , Inc. (also referred to as Company ) and/or its successors and assigns. NOTICE TO USERS WHO ARE NVM Express , INC. MEMBERS: Members of NVM Express , Inc. have the right to use and implement this NVM Express revision specification subject, however, to the Member's continued compliance with the Company's Intellectual Property Policy and Bylaws and the Member's Participation Agreement.

2 NOTICE TO NON-MEMBERS OF NVM Express , INC.: If you are not a Member of NVM Express , Inc. and you have obtained a copy of this document, you only have a right to review this document or make reference to or cite this document. Any such references or citations to this document must acknowledge NVM Express , Inc. copyright ownership of this document. The proper copyright citation or reference is as follows: 2007 - 2014 NVM Express , Inc. ALL RIGHTS RESERVED. When making any such citations or references to this document you are not permitted to revise, alter, modify, make any derivatives of, or otherwise amend the referenced portion of this document in any way without the prior Express written permission of NVM Express , Inc. Nothing contained in this document shall be deemed as granting you any kind of license to implement or use this document or the specification described therein, or any of its contents, either expressly or impliedly, or to any intellectual property owned or controlled by NVM Express , Inc.

3 , including, without limitation, any trademarks of NVM Express , Inc. LEGAL DISCLAIMER: THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS PROVIDED ON AN AS IS . BASIS. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, NVM Express , INC. (ALONG WITH THE CONTRIBUTORS TO THIS DOCUMENT) HEREBY DISCLAIM ALL. REPRESENTATIONS, WARRANTIES AND/OR COVENANTS, EITHER Express OR IMPLIED, STATUTORY OR AT COMMON LAW, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED. WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, VALIDITY, AND/OR NONINFRINGEMENT. All product names, trademarks, registered trademarks, and/or servicemarks may be claimed as the property of their respective owners. NVM Express Workgroup c/o Virtual, Inc. 401 Edgewater Place, Suite 600.

4 Wakefield, MA 01880. 2. NVM Express Table of Contents 1 INTRODUCTION .. 8. Overview .. 8. Scope .. 8. Outside of Scope .. 8. Theory of Operation .. 8. Conventions .. 10. Definitions .. 11. Admin Queue .. 11. arbitration burst .. 11. arbitration mechanism .. 11. candidate command .. 11. command completion .. 11. command 11. Controller .. 11. extended LBA .. 12. firmware slot .. 12. I/O Completion 12. I/O Submission Queue .. 12. LBA range .. 12. logical block .. 12. logical block address (LBA) .. 12. metadata .. 12. namespace .. 12. NVM .. 12. NVM subsystem .. 12. Keywords .. 12. mandatory .. 12. may .. 12. 13. 13. reserved .. 13. shall .. 13. 13. Conventions .. 13. Byte, word and Dword Relationships .. 14. References .. 14. References Under 15.

5 2 SYSTEM BUS (PCI Express ) REGISTERS .. 16. PCI Header .. 16. Offset 00h: ID - Identifiers .. 17. Offset 04h: CMD - Command .. 17. Offset 06h: STS - Device 17. Offset 08h: RID - Revision ID .. 17. Offset 09h: CC - Class Code .. 18. Offset 0Ch: CLS Cache Line Size .. 18. Offset 0Dh: MLT Master Latency Timer .. 18. Offset 0Eh: HTYPE Header Type .. 18. Offset 0Fh: BIST Built In Self Test (Optional) .. 18. Offset 10h: MLBAR (BAR0) Memory Register Base Address, lower 32-bits .. 18. Offset 14h: MUBAR (BAR1) Memory Register Base Address, upper 32-bits .. 18. Offset 18h: IDBAR (BAR2) Index/Data Pair Register Base Address (Optional) .. 19. Offset 1Ch 20h: BAR3 19. Offset 20h 23h: BAR4 Vendor Specific .. 19. Offset 24h 27h: BAR5 Vendor Specific .. 19.

6 Offset 28h: CCPTR CardBus CIS Pointer .. 19. Offset 2Ch: SS - Sub System Identifiers .. 19. 3. NVM Express Offset 30h: EROM Expansion ROM (Optional) .. 19. Offset 34h: CAP Capabilities 19. Offset 3Ch: INTR - Interrupt Information .. 19. Offset 3Eh: MGNT Minimum Grant .. 19. Offset 3Fh: MLAT Maximum Latency .. 20. PCI Power Management Capabilities .. 20. Offset PMCAP: PID - PCI Power Management Capability ID .. 20. Offset PMCAP + 2h: PC PCI Power Management Capabilities .. 20. Offset PMCAP + 4h: PMCS PCI Power Management Control and Status .. 20. Message Signaled Interrupt Capability (Optional) .. 21. Offset MSICAP: MID Message Signaled Interrupt Identifiers .. 21. Offset MSICAP + 2h: MC Message Signaled Interrupt Message Control .. 21. Offset MSICAP + 4h: MA Message Signaled Interrupt Message Address.

7 21. Offset MSICAP + 8h: MUA Message Signaled Interrupt Upper 21. Offset MSICAP + Ch: MD Message Signaled Interrupt Message Data .. 21. Offset MSICAP + 10h: MMASK Message Signaled Interrupt Mask Bits (Optional) .. 21. Offset MSICAP + 14h: MPEND Message Signaled Interrupt Pending Bits (Optional) .. 21. MSI-X Capability (Optional) .. 22. Offset MSIXCAP: MXID MSI-X Identifiers .. 22. Offset MSIXCAP + 2h: MXC MSI-X Message Control .. 22. Offset MSIXCAP + 4h: MTAB MSI-X Table Offset / Table BIR .. 22. Offset MSIXCAP + 8h: MPBA MSI-X PBA Offset / PBA BIR .. 23. PCI Express Capability (Optional) .. 23. Offset PXCAP: PXID PCI Express Capability ID .. 23. Offset PXCAP + 2h: PXCAP PCI Express Capabilities .. 24. Offset PXCAP + 4h: PXDCAP PCI Express Device Capabilities.

8 24. Offset PXCAP + 8h: PXDC PCI Express Device Control .. 24. Offset PXCAP + Ah: PXDS PCI Express Device 25. Offset PXCAP + Ch: PXLCAP PCI Express Link Capabilities .. 25. Offset PXCAP + 10h: PXLC PCI Express Link Control .. 26. Offset PXCAP + 12h: PXLS PCI Express Link Status .. 26. Offset PXCAP + 24h: PXDCAP2 PCI Express Device Capabilities 2 .. 26. Offset PXCAP + 28h: PXDC2 PCI Express Device Control 2 .. 27. Advanced Error Reporting Capability (Optional) .. 27. Offset AERCAP: AERID AER Capability ID .. 28. Offset AERCAP + 4: AERUCES AER Uncorrectable Error Status Register .. 28. Offset AERCAP + 8: AERUCEM AER Uncorrectable Error Mask Register .. 28. Offset AERCAP + Ch: AERUCESEV AER Uncorrectable Error Severity Register .. 29. Offset AERCAP + 10h: AERCS AER Correctable Error Status 29.

9 Offset AERCAP + 14h: AERCEM AER Correctable Error Mask Register .. 30. Offset AERCAP + 18h: AERCC AER Capabilities and Control Register .. 30. Offset AERCAP + 1Ch: AERHL AER Header Log Register .. 31. Offset AERCAP + 38h: AERTLP AER TLP Prefix Log Register (Optional) .. 31. Other Capability Pointers .. 31. 3 Controller REGISTERS .. 32. Register Definition .. 32. Offset 00h: CAP Controller Capabilities .. 34. Offset 08h: VS Version .. 35. Offset 0Ch: INTMS Interrupt Mask Set .. 35. Offset 10h: INTMC Interrupt Mask Clear .. 35. Offset 14h: CC Controller Configuration .. 35. Offset 1Ch: CSTS Controller Status .. 37. Offset 24h: AQA Admin Queue Attributes .. 38. Offset 28h: ASQ Admin Submission Queue Base Address .. 38. Offset 30h: ACQ Admin Completion Queue Base Address.

10 38. Offset (1000h + ((2y) * (4 << ))): SQyTDBL Submission Queue y Tail Doorbell .. 38. Offset (1000h + ((2y + 1) * (4 << ))): CQyHDBL Completion Queue y Head Doorbell .. 39. Index/Data Pair registers (Optional) .. 39. Restrictions .. 39. Register Definition .. 39. 4. NVM Express Offset 00h: IDX Index Register .. 40. Offset 04h: DAT Data Register .. 40. 4 SYSTEM Memory STRUCTURES .. 41. Submission Queue & Completion Queue Definition .. 41. Empty Queue .. 41. Full Queue .. 42. Queue Size .. 42. Queue Identifier .. 42. Queue Priority .. 43. Submission Queue Entry Command Format .. 43. Physical Region Page Entry and List .. 45. Metadata Region (MR) .. 46. Completion Queue Entry .. 46. Status Field Definition .. 47. Fused Operations .. 50. Command Arbitration.