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Octal 8-Bit Digital-to-Analog Converters (Rev. E

TLC5628C, TLC5628 IOCTAL 8-Bit Digital-to-Analog Converters SLAS089E NOVEMBER 1994 REVISED APRIL 19971 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 DEight 8-Bit Voltage Output DACsD5-V Single-Supply OperationDSerial InterfaceDHigh-Impedance Reference InputsDProgrammable 1 or 2 Times Output RangeDSimultaneous Update FacilityDInternal Power-On ResetDLow-Power ConsumptionDHalf-Buffered OutputapplicationsDProgrammable Voltage SourcesDDigitally Controlled Amplifiers/AttenuatorsDMobile CommunicationsDAutomatic Test EquipmentDProcess Monitoring and ControlDSignal Synthesis descriptionThe TLC5628C and TLC5628I are Octal 8-Bit voltage output Digital-to-Analog Converters (DACs) with bufferedreference inputs (high impedance).

tlc5628c, tlc5628i octal 8-bit digital-to-analog converters slas089e – november 1994 – revised april 1997 post office box 655303 • dallas, texas 75265 3 detailed description

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Transcription of Octal 8-Bit Digital-to-Analog Converters (Rev. E

1 TLC5628C, TLC5628 IOCTAL 8-Bit Digital-to-Analog Converters SLAS089E NOVEMBER 1994 REVISED APRIL 19971 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 DEight 8-Bit Voltage Output DACsD5-V Single-Supply OperationDSerial InterfaceDHigh-Impedance Reference InputsDProgrammable 1 or 2 Times Output RangeDSimultaneous Update FacilityDInternal Power-On ResetDLow-Power ConsumptionDHalf-Buffered OutputapplicationsDProgrammable Voltage SourcesDDigitally Controlled Amplifiers/AttenuatorsDMobile CommunicationsDAutomatic Test EquipmentDProcess Monitoring and ControlDSignal Synthesis descriptionThe TLC5628C and TLC5628I are Octal 8-Bit voltage output Digital-to-Analog Converters (DACs) with bufferedreference inputs (high impedance).

2 The DACs produce an output voltage that ranges between either one or twotimes the reference voltages and GND and are monotonic. The device is simple to use, running from a singlesupply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up control of the TLC5628C and TLC5628I are over a simple three-wire serial bus that is CMOS compatibleand easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command wordcomprises eight bits of data, three DAC select bits, and a range bit, the latter allowing selection between thetimes 1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new valuesto be written to the device, then all DAC outputs are updated simultaneously through control of LDAC.

3 The digitalinputs feature Schmitt triggers for high-noise 16-terminal small-outline (D) package allows digital control of analog functions in space-criticalapplications. The TLC5628C is characterized for operation from 0 C to 70 C. The TLC5628I is characterizedfor operation from 40 C to 85 C. The TLC5628C and TLC5628I do not require external OPTIONSPACKAGETASMALL OUTLINE(DW)PLASTIC DIP(N)0 C to 70 CTLC5628 CDWTLC5628CN 40 C to 85 CTLC5628 IDWTLC5628 INPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

4 PRODUCTION DATA information is current as of publication conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all 1997, Texas Instruments Incorporated1234 5678161514131211109 DACBDACAGNDDATACLKVDDDACEDACFDACCDACDREF 1 LDACLOADREF2 DACHDACGN OR DW PACKAGE(TOP VIEW)TLC5628C, TLC5628 IOCTAL 8-Bit Digital-to-Analog Converters SLAS089E NOVEMBER 1994 REVISED APRIL 19972 POST OFFICE BOX 655303 DALLAS, TEXAS 75265functional block diagramSerialInterface 2 DACDAC 2 2 DACDAC 2 LDACREF1+ + + + + + REF2 CLKDATALOADDACADACDDACEDACH98888 LatchLatchLatchLatchLatchLatchLatchLatch Power-OnReset1411541213215710 Terminal interface clock.

5 The input digital data is shifted into the serial interface register on the falling edge of the clockapplied to the CLK A analog outputDACB1 ODAC B analog outputDACC16 ODAC C analog outputDACD15 ODAC D analog outputDACE7 ODAC E analog outputDACF8 ODAC F analog outputDACG9 ODAC G analog outputDACH10 ODAC H analog outputDATA4 ISerial interface digital data input. The digital code for the DAC is clocked into the serial interface register data bit is clocked into the register on the falling edge of the clock return and reference terminalLDAC13 ILoad DAC. When LDAC is high, no DAC output updates occur when the input digital data is read into the serialinterface.

6 The DAC outputs are only updated when LDAC is taken from high to interface load control. When LDAC is low, the falling edge of the LOAD signal latches the digital data intothe output latch and immediately produces the analog voltage at the DAC output voltage input to DAC A B C D. This voltage defines the analog output voltage input to DAC E F G H. This voltage defines the analog output supply voltageTLC5628C, TLC5628 IOCTAL 8-Bit Digital-to-Analog Converters SLAS089E NOVEMBER 1994 REVISED APRIL 19973 POST OFFICE BOX 655303 DALLAS, TEXAS 75265detailed descriptionThe TLC5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with256 taps, corresponding to the 256 possible codes listed in Table 1.

7 One end of each resistor string is connectedto GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by useof the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performanceof the output buffer. Since the inputs are buffered, the DACs always present a high-impedance load to thereference sources. There are two input reference terminals; REF1 is used for DACA through DACD and REF2is used by DACE through DAC output is buffered by a configurable-gain output amplifier, that can be programmed to times 1 or times2 power up, the DACs are reset to CODE output voltage is given by:VO(DACA|B|C|D|E|F|G|H)+REF CODE256 (1)RNG bit value)where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control 1.

8 Ideal Output TransferD7D6D5D4D3D2D1D0 OUTPUT VOLTAGE00000000 GND00000001(1/256) REF (1+RNG) 01111111(127/256) REF (1+RNG)10000000(128/256) REF (1+RNG) 11111111(255/256) REF (1+RNG)data interfaceWith LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits havebeen clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC asshown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. WhenLDAC is high during serial programming, the new value is stored within the device and can be transferred tothe DAC output at a later time by pulsing LDAC low as shown in Figure 2.

9 Data is entered most significant bit(MSB) first. Data transfers using two 8-clock cycle periods are shown in Figures 3 and UpdateCLKDATALOADtsu(DATA-CLK)tv(DATA-CL K)tsu(CLK-LOAD)tw(LOAD)tsu(LOAD-CLK)Figu re 1. LOAD-Controlled Update (LDAC = Low)TLC5628C, TLC5628 IOCTAL 8-Bit Digital-to-Analog Converters SLAS089E NOVEMBER 1994 REVISED APRIL 19974 POST OFFICE BOX 655303 DALLAS, TEXAS 75265data interface (continued)CLKDATALOADLDACDAC UpdateA2A1A0 RNGD7D6D5D4D2D1D0tsu(DATA-CLK)tv(DATA-CL K)tw(LDAC)tsu(LOAD LDAC)Figure 2. LDAC-Controlled Update A1A0 RNGD7D6D5D4D3D2D1D0 CLKDATALOADLDACCLK LowA2 Figure 3. Load-Controlled Update Using 8-Bit Serial Word (LDAC = Low) A1A0 RNGD7D6D5D4D3D2D1D0 CLKDATALOADLDACCLK LowA2 Figure 4.

10 LDAC-Controlled Update Using 8-Bit Serial WordTable 2 lists the A2, A1, and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC outputrange. When RNG = low, the output range is between the applied reference voltage and GND, and whenRNG = high, the range is between twice the applied reference voltage and 2. Serial Input DecodeA2A1A0 DAC UPDATED000 DACA001 DACB010 DACC011 DACD100 DACE101 DACF110 DACG111 DACHTLC5628C, TLC5628 IOCTAL 8-Bit Digital-to-Analog Converters SLAS089E NOVEMBER 1994 REVISED APRIL 19975 POST OFFICE BOX 655303 DALLAS, TEXAS 75265linearity, offset, and gain error using single-end suppliesWhen an amplifier is operated from a single supply, the voltage offset can still be either positive or negative.


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