Transcription of Operation and Benefits of Active-Clamp Forward Power ...
1 LM5025,LM5026,LM5034. Operation and Benefits of Active-Clamp Forward Power Converters Literature Number: SNVA591. Power designer Expert tips, tricks, and techniques for powerful designs No. 108. Operation and Benefits of Active-Clamp Feature Forward Power Converters Dual Interleaved active - Bob Bell, Power Applications Engineer Clamp Current-Mode Controller ..2 VOUT = D x V. V IN IN. Active-Clamp Current- BUCK VOUT. Q1 L1. Mode PWM D1. Half-Bridge Power C1. D* Ts MOSFET Ts Power Design VIN. VOUT. D2 L1. Forward Np Ns D1. C1. Q1. VOUT = D x Ns x VIN. Np Figure 1. Buck and Forward Topologies F. orward converters with Active-Clamp reset offer multiple Benefits to designers and are presently finding wide use. Power converters based on the Forward topology are an excellent choice for applications where high efficiency and good Power handling capability is required in the 50 to 500W Power range.
2 While the popularity of Forward topology is based upon many factors, designers have been primarily drawn to it's simplicity, performance, and efficiency. The Forward converter is derived from the buck topology. The main difference between the two topologies is that the transformer employed in the Forward topology provides input-output ground isolation as well as a step-down or step-up function. The transformer in a Forward topology does not inherently reset each switching cycle as do symmetrical topologies (push-pull, half- bridge, and full-bridge). A number of different reset mechanisms have been employed in Forward Power converters, each method has its own Benefits and challenges. Forward converters with Active-Clamp reset offer multiple Benefits to designers and are presently finding wide use. NEXT ISSUE: Low- Power FPGA Designs 100V Dual Interleaved Active-Clamp Current-Mode Controller Highly Integrated LM5034 Maximizes Efficiency and Power Density of DC-DC.
3 Converters Features LM5034 Interleaved Forward active Clamp Converter Independent current-mode controllers 48V In Rectifier Interleaved single or dual output Operation and Filter Start-up Compound main FET gate drivers Regulator Current Gate Drivers Mode UVLO PWM. active clamp FET gate drivers Ch. 1. Out 48V Rectifier Integrated 100V start-up regulator Oscillator Timing Control and Filter Up to 1 MHz switching frequency Hiccup Current Mode PWM. Gate Drivers Mode programmed by a single resistor Ch. 2. Feedback and Programmable maximum duty cycle Isolation Adjustable soft-start and input under- voltage sensing Adjustable deadtime between main and LM5034 Efficiency Graph active clamp gate drivers 100. Available in TSSOP-20 packaging 95. Vin = 36V. Efficiency (%). 90. Vin = 48V. Ideal for telecom infrastructure, networking, industrial, and automotive Power supplies 85.
4 Vin = 78V. Vout = 80. Product Highlight: 75. 0 10 20 30 40 50 60. LM5034 enables high efficiency in Load Current (A). 200W to 500W DC-DC converters while reducing input ripple 2. Power designer Operation and Benefits of Active-Clamp Forward Power Converters Lm with the secondary winding(s) shorted. This term represents the stray primary inductance, which is not coupled to the secondary. Active-Clamp Circuit Operation Primary Ns Np Secondary Figures 3a through 3c illustrate the main operational steps of an active clamp Forward Power converter. At time t0, the main Power switch (Q1). is on, applying VIN across the transformer primary. LL. Ideal Transformer The transformer secondary winding voltage is VIN x Ns/Np. The primary current is comprised of Figure 2. Transformer Model two components at this time; the reflected current from the output inductor (IL x Ns/Np) and the Figure 1 shows the similarities between a buck and current ramping up in the magnetizing inductance Forward converter.
5 Note the only difference between (Lm). The reset switch Q2 is open and the clamp the transfer functions is the inclusion of the turns capacitor (Cc) has been previously charged to a ratio term (Ns/Np) in the Forward transfer func- voltage of VIN/(1-D), which will be explained later. tion. Ns and Np are the number of secondary and This interval is the Power phase, energy is primary turns, wound on the transformer core. transferred from the primary to the secondary Figure 2 presents a transformer model, including the during this period. The approximate duration of Magnetizing Inductance (Lm) shown in parallel the Power phase is Ts x VOUT / VIN, where Ts is the with the primary winding. This magnetizing induc- switching period. tance can be measured at the primary terminals with At time t1, the main Power switch (Q1) is turned the secondary winding(s) open circuit.
6 The current in off and the reset switch (Q2) is turned on. The the magnetizing inductance is proportional to the magnetizing current flows through the clamp flux density within the core. A given size core can capacitor and Q2 instead of through Q1. Since the only support a certain flux density before saturation clamp capacitor voltage is greater than VIN, the of the core occurs. When the core saturates, there is a voltage across the transformer primary is now rapid reduction in inductance. Another element of reversed, compared to the Power phase t0. Because the transformer model is the Leakage Inductance the potential across the magnetizing inductance has (LL) in series with the primary winding. This leakage been reversed, the magnitude of the magnetizing inductance can be measured at the primary terminals current will decrease as the energy stored in the VIN VIN T1.
7 T1. L1 VOUT L1 VOUT. + . Lm D2 Lm D2. Np Ns D1 C1 Np Ns D1 C1. +. 0V V in Cc (1 -D ) Cc Q1 Q2 Q1 Q2. Figure 3a. Operation at Step t0 Figure 3b. Operation at Step t1. 3. Current-Mode Controller for Forward Converters with Active-Clamp Reset LM5026 Offers Versatile Dual-Mode Over-Current Protection with Hiccup Delay Timer Features LM5026 Typical Application Circuit Wide range (8V to 100V) start-up bias 48V In regulator Two high-speed Power MOSFET drivers: UVLO Soft-start Restart Rectifier Out and Filter 3A main output driver and 1A clamp driver Oscillator Current User-programmable maximum duty-cycle Current Sense Mode and UVLO hysteresis thresholds Start-up Regulator PWM Main and Clamp User-programmable gate driver overlap Gate Drivers and dead-time 5V Reference Feedback I to V Converter and Versatile dual-mode over-current PWM Control Isolation Current protection with hiccup mode delay timer TSSOP-16 or thermally enhanced LLP-16.
8 Packaging Hiccup Over-Load Restart Timing Ideal for use in telecommunications Power systems, +42V automotive Power systems, -48V distributed Power systems, industrial Current Limit Detected Power supplies, and multi-output Power RES. supplies OV. SS 50 A. 1 A. ~= OUTA. Product Highlight: t1 t2 t3. Robust and flexible Forward Active-Clamp controller offers highest efficiency 4. Power designer Operation and Benefits of Active-Clamp Forward Power Converters VIN through the reset switch (Q2) and the magnetizing T1. L1 VOUT inductance (Lm) then back to the source (VIN).. Lm D2 The current will continue to build in the opposite Np Ns D1 C1 direction as the clamp capacitor returns the energy +. that it had previously captured from the magnetizing inductance. Steady state conditions require the V in (1 -D ) Cc clamp capacitor voltage to return to the starting potential and the magnetizing current at the Q2.
9 Q1 conclusion of the reset time to reach the same magnitude (opposite polarity) as the current at the beginning of this reset time. At the conclusion of t2, the switching period is over, as defined by the Figure 3c. Operation at Step t2 controller oscillator period. The reset switch is turned off, stopping the flow of current from the magnetizing inductance is transferred into the clamp capacitor. clamp capacitor. The voltage across the clamp Figure 4 shows several of the key circuit waveforms. capacitor increases slightly during this period and The uppermost waveforms are the modulator ramp peaks when the magnetizing current reaches zero. and error signals which determine the main switch At t2, the current in the magnetizing inductance on-time. The center waveform is the main switch reaches zero and starts to build in the opposite drain voltage, which is low when the switch is on direction, sourced from the clamp capacitor and rises to the clamp capacitor potential when the 6.
10 4. Controller Ramp 2. and Error Signal (V). 0. -2. 125. 100. 75. Main Switch 50. Drain Voltage (V) 25. 0. -25. 200. 100. Clamp Cap and Magnetizing Current (mA) 0. -100. -200. TIME. Figure 4. Key Active-Clamp Waveforms 5. 100V Half-Bridge Power MOSFET Drivers LM510x Family Offers the Industry's Highest Peak Gate Drive Current LM510x Typical Application Circuit 10V to 100V. (Integrated bootstrap). +10V VDD HB. F F. HO. UVLO Driver HS. HI. Level shift LM50xx PWM. Load controller or UVLO. microprocessor LO. LI Driver VSS. Features Flexible configurations: interleaved Forward , Ideal for half-bridge and full-bridge Power cascaded push-pull, half-bridge or full-bridge DC-DC converters, cascading current-fed or User-programmable turn-on edge delay feature voltage-fed DC-DC converters, high-voltage (LM5105) buck DC-DC converters, and solid-state motor and solenoid drivers New high-voltage bootstrap diode Best-in-class speed and efficiency in high-fre- quency switching regulator applications Family Highlight: Negative load voltage transient capability down Synchronous gate drivers optimized for every to 5V (LM5105/07) topology and high efficiency Available in SOIC and tiny, thermally enhanced LLP packaging Peak Gate Product ID Input Threshold Packaging Comments Current NE.