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Overview of SOC Architecture design

SOC - 0 by Tien-Fu Chen@CCUO verview of SOCA rchitecture designTien-Fu ChenNational Chung Cheng ArchitecturesSOC - 1 by Tien-Fu Chen@CCUSOC design Issues SOC Architecture Reconfigurable System-level Programmable processors Low-level reconfiguration On-chip bus Embedded Software IssuesSOC - 2 by Tien-Fu Chen@CCUE mbedded Systems vs. General PurposeComputing - 1 Embedded System Runs a few applications oftenknownatdesigntime Not end-user programmable Operates in fixed run-timeconstraints, additional performancemay not be useful/valuable General purpose computing Intended to run a fully general setof applications End-user programmable Faster is always betterSOC - 3 by Tien-Fu Chen@CCUE mbedded Systems vs. General PurposeComputing - 2 Embedded System Differentiating features: power cost speed (must be predictable) General purpose computing Differentiating features speed (need not be fullypredictable) speed did we mention speed?

System Architecture Design System Architecture & Exploration What Hardware/Software partitioning; processor, and memory architecture choices; system timing budget, power management strategy, system verification strategy… Partitioning into HW block hierarchy, cycle time budgeting, block interfaces, block verification, clock architecture and ...

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Transcription of Overview of SOC Architecture design

1 SOC - 0 by Tien-Fu Chen@CCUO verview of SOCA rchitecture designTien-Fu ChenNational Chung Cheng ArchitecturesSOC - 1 by Tien-Fu Chen@CCUSOC design Issues SOC Architecture Reconfigurable System-level Programmable processors Low-level reconfiguration On-chip bus Embedded Software IssuesSOC - 2 by Tien-Fu Chen@CCUE mbedded Systems vs. General PurposeComputing - 1 Embedded System Runs a few applications oftenknownatdesigntime Not end-user programmable Operates in fixed run-timeconstraints, additional performancemay not be useful/valuable General purpose computing Intended to run a fully general setof applications End-user programmable Faster is always betterSOC - 3 by Tien-Fu Chen@CCUE mbedded Systems vs. General PurposeComputing - 2 Embedded System Differentiating features: power cost speed (must be predictable) General purpose computing Differentiating features speed (need not be fullypredictable) speed did we mention speed?

2 Cost (largest component power)CPUmeminputoutputanaloganalogembed dedcomputerLogicSOC - 4 by Tien-Fu Chen@CCUE mbedded System: ExamplesEmbeddedSystemSOC - 5 by Tien-Fu Chen@CCUD esign Complexity Increase35%12%25%10%>5 Clock Domains>9 Clock Domains61%22%44%15%Clock Speed >133mhz>400mhz295K266K54K75K# of lines of DSP SW# of lines of uP SW37%20%Units Shipped >5M1,000K31%616K18%Average Gate CountDesigns with Gate Count >1 MNextDesignCurrentDesignSoC CharacteristicsSource: Collett International Research- December 2000 Research on360 IC/ASIC design Teams in North AmericaSOC - 6 by Tien-Fu Chen@CCUI mplementationTimed,Clocked,RTL LevelRefinementDesign ExportSpecificationUntimed,Unclocked,C/C ++ LevelEmbedded System on Chip (SoC) DesignTestbenchSatelliteMacro-CellMicro- CellZone 2: UrbanZone 1: In-BuildingPico-CellZone 4: GlobalZone 3: SuburbanSystemEnvironmentImplementationC haracterizationFirmwareCORES oftwareSOC P/CAnalogEmbeddedSoftwareMemoryEmbeddedS ystems DesignRequirementsSpecificationSOC - 7 by Tien-Fu Chen@CCUA rchitectures SupplementsModelsby specifying how the system willactually be implemented Goal of each Architecture is to describe Number of components Type of each component Type of each connection among above components General classification Application-specific architectures: DSP General-purpose architectures: CISC, RISC Parallel processors: VLIW, SIMD, MIMDSOC - 8 by Tien-Fu Chen@CCUS ystem Architecture design System Architecture & Exploration What Hardware/Software partitioning; processor, and memory architecturechoices.

3 System timing budget, power management strategy, systemverification Partitioning into HW block hierarchy, cycle time budgeting, blockinterfaces, block verification, clock Architecture and test strategy Fixed point Architecture exploration and design How - Quickly assemble Architecture (s) for exploration tomeasure system timing/performance. Need to accurately(enough) model the bottlenecksSOC - 9 by Tien-Fu Chen@CCUS ystem Integration & Verification System design Environment for HW/SW Refinement,Verification and Integration What Enables hierarchical (manual or automatic) refinement of individual blocks ofdesign in context of system. Maintain system and hierarchical test benches Verification of refined hardware/software with entire system design Define next level of clock Architecture (derived) and test strategy How - Build a system verification hierarchy that allowsintegration of HW blocks, system software (HAL), embeddedapplication SW and eventually verifying the entire design atcycle accurate (or RTL) levelSOC - 10 by Tien-Fu Chen@CCUCoDesign and Co-SynthesisSpecificationDetailed Representationof ImplementationSynthesisHW:HDL(Behavioral , DataFlow, Structural), SchematicRTL, Gate level, Transistors, LayoutSW:Algorithm,Textual/Graphical representationExecutable or Compilable code.

4 The program(s), OS routinesCo-SynthesisPartitionSOC - 11 by Tien-Fu Chen@CCUF abricationTestTraditional designSystemdesignASIC designSW designPCB testSW testTimeTasksTraditional System design ProcessSOC - 12 by Tien-Fu Chen@CCUS ystem-level Co-designShared DesignCo- design ProcessSW designASIC designFabricationTestPCB testSW testTimeTasksSystemdesignSystem-Level PartitioningSOC - 13 by Tien-Fu Chen@CCUC onfigurabilty and Embedded Systems Advantages of configuration: Pay (in power, design time, area) only for what youuse Gain additional performance by adding featurestailored to your application: Particularly for embedded systems: Principally in embedded controller microprocessorapplications Some us in DSPSOC - 14 by Tien-Fu Chen@CCUWhat to Configure? What parts of the microcontroller/microprocessor system toconfigure? Easy answers: Memory and Cache Sizes - get precisely the sizes your applicationsneeds Register file sizes Interrupt handling and addresses Harder answers: Peripherals Instructions But first we need more contextSOC - 15 by Tien-Fu Chen@CCUT rickle Down Theory of Embedded Architectures Mainframe/supercomputers High-end servers/workstations High-end personal computers Personal computers Lap tops/palm tops Gadgets Watches.

5 Features tend to trickle down: #bits: 4->8->16->32->64 ISA s Floating point support Dynamic scheduling Caches I/O controllers/processors LIW/VLIW SuperscalarSOC - 16 by Tien-Fu Chen@CCUC onfigurability in ARM Processor ARM allows for configurability via AMBA bus Offers ``prime cell peripherals which hook into AMBA PeripheralBus (APB) UART Real Time Clock Audio Codec Interface Keyboard and mouse interface General purpose I/O Smart card interface Generic IR interfaceSOC - 17 by Tien-Fu Chen@CCUARM7 coreSOC - 18 by Tien-Fu Chen@CCUARM s Amba open standard Advanced System Bus, (ASB) - high performance, CPU, DMA, external Advanced Peripheral Bus, (APB) - low speed, low power, parallel I/O,UART s External #introSOC - 19 by Tien-Fu Chen@CCUEx: ARM Infrared (IR)InterfaceSOC - 20 by Tien-Fu Chen@CCUEx : Audio CodecSOC - 21 by Tien-Fu Chen@CCUA nother Kind of ConfigurabilityRTLS ynthesisHDLnetlistlogicoptimizationnetli stLibraryphysicaldesignlayoutSynthesis of a processor core froman RTL description allows for: full range of other types ofconfigurability additional degrees of freedom inquality of implementationExamples.

6 ARM7 Motorola Coldfire Tensilica XtensaSOC - 22 by Tien-Fu Chen@CCUI ssues in low-level Configurable design Choice and Granularity of ComputationalElements Choice and Granularity of InterconnectNetwork (Re)configuration Time and Rate Fabrication time --> Fixed function devices Beginning of product use --> Actel/QuicklogicFPGAs Beginning of usage epoch --> (Re)configurableFPGAs Every cycle --> traditional Instruction SetProcessorsSOC - 23 by Tien-Fu Chen@CCUThe Choice of the Computational ElementsReconfigurableReconfigurableLogi cLogicReconfigurableReconfigurableDatapa thsDatapathsadderbufferreg0reg1muxCLBCLB CLBCLBDataMemoryIn s t ru c tio nDecoder&C ontrollerDataMemoryProgramMemoryDatapath MACInAddrGenMemoryAddrGenMem oryReconfigurableReconfigurableArithmeti cArithmeticReconfigurableReconfigurableC ontrolControlBit-Level encodingDedicated data Filters, AGUA rithmetic ConvolutionRTOSP rocess managementSOC - 24 by Tien-Fu Chen@CCUM ulti-granularity Reconfigurable Architecture .

7 The Berkeley Pleiades ArchitectureCommunication NetworkControlProcessorArithmeticProcess orArithmeticProcessorArithmeticProcessor ConfigurableDatapathConfigurableLogicCon figuration BusNetwork InterfaceDedicatedArithmeticConfiguratio nSatellite ProcessorSatellite Processor Computational kernels are spawned to satellite processors Control processor supports RTOS and reconfiguration Order(s) of magnitude energy-reduction over traditional programmable architecturesSOC - 25 by Tien-Fu Chen@CCUM atching Computation and ArchitectureAddressGenAddressGenMemoryMe moryMACMACC ontrolProcessorLCGC onvolutionTwo models of computation:communicating processes + data-flowTwo architectural models:sequential control+ data-drivenSOC - 26 by Tien-Fu Chen@CCUE xecution Model of a Data-Flow Kernelfor(i=1;i<=L;i++)for(k=i;k<=L;k++) phi[i][k]= phi[i-1][k-1]+in[NP-i]*in[NP-k]-in[NA-1- i]*in[NA-1-k];endstartEmbedded processorAddrGenMEM: inALUALUAddrGenMEM: phiMPYMPY Distributed control and memoryCode segCode segSOC - 27 by Tien-Fu Chen@CCUS oftware Methodology FlowAlgorithmsKern el Dete ctionEstimation/ExplorationPartitioningS oftware CompilationReconfig.

8 Hardware MappingInte rface Cod e G en eratio nPo wer & Timing Estimationof Vario us Kernel Implemen tationsPDA ModelsPremappedKernelsAccelerator proc&BehavioralC++ M od uleLibrariesC++SUIF+ C-IFSOC - 28 by Tien-Fu Chen@CCUThe System-on-a-Chip BusPeripheralBusControl WiresCustom InterfacesThe Board-on-a-Chip ApproachSOC - 29 by Tien-Fu Chen@CCUS onics SOC Integration ArchitectureSiliconBackplaneAgent Open CoreProtocol SiliconBackplane (patented)MultiChipBackplane {DSPMPEGCPUDMACMEMIOSOC - 30 by Tien-Fu Chen@CCUM aster vs. SlaveIP CoreIP CoreIP CoreOn-Chip BusSlaveMasterSlaveSlaveSlaveMasterMaste rMasterInitiatorTargetOpen CoreProtocolRequestResponseSOC - 31 by Tien-Fu Chen@CCUThe Backplane: Why Not Use a Computer Bus?IPCoreIPCore IPCoreIPCore ComputerBusTransmit FIFOR eceive FIFOTimeDataArbiterAddress Expensive to decouple Not designed for real-timeSOC - 32 by Tien-Fu Chen@CCUC ommunication Buses Decoupleand Guarantee Real TimeIPCoreIPCore IPCoreIPCore CommunicationsBusTransmit FIFOR eceive FIFOTimeDataTDMATDMA Connections are expensive Poor read latencySOC - 33 by Tien-Fu Chen@CCUOn-Chip Bus for SOC Example on- chip bus interconnects ARM s AMBA bus IBM s Core Connect Virtual Socket Interface Alliance group Open Connect Protocol group Example processor cores ARM MIPS PowerPCSOC - 34 by Tien-Fu Chen@CCUR econfigurableDataPathReconfigurableState MachinesEmbeddeduP+DSPsFPGAD edicatedDSPD esign Example.}

9 The Radio-on-a-Chip DSP and controlintensive Mixed-mode Combinesprogrammable, flexible,and application-specificmodules Cost and energy arethe key metricsSOC - 35 by Tien-Fu Chen@CCUS ystem Level design Science design Methodology: Top Down Aspect: Orthogonalization of Concerns: Separate Implementation from Conceptual AspectsSeparate Implementation from Conceptual Aspects Separate computation from communicationSeparate computation from communication Formalization: precise unambiguous semantics Abstraction: capture the desired system details (do not overspecify) Decomposition: partitioning the system behavior into simpler behaviors Successive Refinements: refine the abstraction level down to theimplementation by filling in details and passing constraints Bottom Up Aspect: IP Re-use (even at the algorithmic and functional level) Components of Architecture from pre-existing librarySOC - 36 by Tien-Fu Chen@CCUS eparate Behavior from Micro-architectureFrontFrontEndEnd11 TransportTransportDecodeDecode22 RateRateBufferBuffer1212 RateRateBufferBuffer99 RateRateBufferBuffer55 SensorSensorSynchSynchControlControl44 VideoVideoDecodeDecode66 AudioAudioDecode/Decode/OutputOutput1010 MemMem1111 User/SysUser/SysControlControl33 MemMem1313 FrameFrameBufferBuffer77 VideoVideoOutputOutput88 System Behavior Functional Specificationof System.

10 No notion of hardware orsoftware! Implementation Architecture Hardware and Software Optimized ComputerDSP RAMDSP RAME xternalExternalI/OI/OSystemSystemRAMRAMD SPDSPP rocessorProcessorProcessor BusProcessor BusControlControlProcessorProcessorMPEGM PEGP eripheralPeripheralAudioAudioDecodeDecod eSOC - 37 by Tien-Fu Chen@CCUMap Between Behavior from ArchitectureFrontFrontEndEnd11 TransportTransportDecodeDecode22 RateRateBufferBuffer1212 RateRateBufferBuffer99 RateRateBufferBuffer55 SensorSensorSynchSynchControlControl44 VideoVideoDecodeDecode66 AudioAudioDecode/Decode/OutputOutput1010 MemMem1111 User/SysUser/SysControlControl33 MemMem1313 FrameFrameBufferBuffer77 VideoVideoOutputOutput88 Audio Decode BehaviorImplemented onDedicated HardwareTransport Decode Implementedas Software Task Runningon MicrocontrollerDSP RAMDSP RAME xternalExternalI/OI/OSystemSystemRAMRAMD SPDSPP


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