PC SDRAM Serial Presence Detect (SPD) Specification

1 PC SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 1 of 28 Revision SDRAM Serial Presence Detect (SPD)SpecificationREVISION , 1997PC SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 2 of 28 Revision Specification IS PROVIDED "AS IS" WITH NO WARRANTIESWHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANYWARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, Specification ORSAMPLE. Intel disclaims all liability, including liability for infringement of any proprietaryrights, relating to use of information in this Specification . No license, express or implied,by estoppel or otherwise, to any intellectual property rights is granted herein.

2 * *Third-party brands and names are the property of their respective Intel Corporation, 1997PC SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 3 of 28 Revision :Revision :Modified Specification nameCorrects the typos in revision historyByte 127 bit 3 definition reserved for thermal information, values are TBDR evision adds:Bytes 126, 127: Additional Information for backward compatibility Bytes 93-94:Manufacturing Date CodeBytes 32-35: Additional Timing InformationByte 5: Changed the nomenclature from Bank to Row on the DIMM to removeconfusion of Rows vs. Banks on a DIMMR evision adds comments to clarify several Bytes:Bytes 3-4: Note added to clarify address row/column 1/16 rollup 5,17: Note added to clarify Module, SDRAM Device bank 23-26: Note added to clarify timing1/16ns rollup SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 4 of 28 Revision OF CONTENTSCHANGE HISTORY3 LIST OF TABLES4 LIST OF SDRAM MODULE PERFORMANCE eeprom COMPONENT Serial Presence Detect eeprom DATA11 LIST OF TABLESTABLE 1: eeprom COMPONENT TIMING PARAMETERS8 TABLE 2: Serial Presence Detect DATA FORMAT13 LIST OF FIGURESFIGURE 1: eeprom COMPONENT TIMING PARAMETERS9 FIGURE 2: eeprom DATA VALIDITY10 FIGURE 3: eeprom START AND STOP CONDITIONS10 FIGURE 4.

3 eeprom ACKNOWLEDGE10 FIGURE 5: eeprom BYTE WRITE OPERATION11 FIGURE 6: eeprom PAGE WRITE OPERATION11 FIGURE 7: eeprom CURRENT ADDRESS READ OPERATION11 FIGURE 8: eeprom RANDOM READ OPERATION11 FIGURE 9: eeprom SEQUENTIAL READ OPERATION12PC SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 5 of 28 Revision IntroductionThis Specification defines the Serial Presence Detect (SPD) electrical and Data Structurerequirements for Synchronous DRAM Dual In-Line Memory Modules ( SDRAM DIMMs) andSmall-outline Memory Modules (SO-DIMM). These SDRAM DIMMs are intended for use asmain memory installed on personal computer, work-station, and/or server referenceThis Specification largely follows the JEDEC defined 168-pin and SO-144 SDRAM DIMM SPDspecs as of July 1996.

4 Changes in process are currently shown in SDRAM Module Performance GradesThree performance grades are defined in the SPD matrix:CAS Latency xhighest latency, lowest performanceCAS Latency x-12nd highest latencyCAS Latency x-23rd highest latency, highest performance (may restrict freq)This is a relative series of three latencies, CL x being the most commonly available at thisspeed performance grade of the module is determined by the read data access time (Tac), andRAS cycle time (Trc) supported by the SDRAM numbers in the sequence will depend on the speeds which are supported by SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 6 of 28 Revision eeprom Component SpecificationsThe Serial Presence Detect function is implemented using a 2048 bit eeprom component.

5 Thisnonvolatile storage device contains data programmed by the DIMM manufacturer that identifiesthe module type and various SDRAM organization and timing parameters. System read/writeoperations to the eeprom device occur using the DIMM s SCL (clock) and SDA (data)signals, together with SA(2:0) which provide the eeprom Device Address. If the eeprom device has a Write Protect input pin, it must be tied in the non-write protect state on the DIMMPCB. The eeprom device selected by the DIMM manufacturer must use the SA(2:0) deviceaddress signals. The eeprom must operate with a VCC of Vdc to 1: eeprom Component Absolute Maximum RatingsParameterRangeAll Input or Output Voltages withRespect to Ground+ to Storage Temperature-40 oC to +100 oCTable2: eeprom Component Operating ConditionsParameterRangeAmbient Operating Temperature0 oC to +70 oCPositive Power to 3: eeprom Component and CharacteristicsSymbolParameterTest ConditionsMinMaxUnitsICCAA ctive Power Supply CurrentfSCL = 100 CurrentVIN = GND or VCC100uAILII nput Leakage CurrentVIN = GND or VCC10uAILOO utput Leakage CurrentVOUT = GND to VCC10uAVILI nput Low X High VoltageVCC X Low VoltageIOL = SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 7 of 28 Revision 4.

6 eeprom Component Timing ParametersSymbolParameterMinMaxUnitsfSCL SCL Clock Frequency80kHzTINoise Supression Time Constant atSCL, SDA inputs100nstAASCL Low to SDA Data Out the Bus Must Be Free before aNew Transmission Can :STAS tart Condition Hold Low High :STAS tart Condition Setup Time(for a Repeated Start Condition) :DATData In Hold Time0ustSU:DATData In Setup Time5001nstRSDA and SCL Rise Time1ustFSDA and SCL Fall Time300nstSU:STOStop Condition Setup Out Hold Time300nstWRWrite Cycle Time15msNote: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of theEEPROM internal erase/program cycle. During the write cycle, the eeprom bus interface circuits aredisabled, SDA remains high due to pull-up resistor, and the eeprom does not respond to its :STAtHD:STAtSU:DATtSU:STOtBUFtDHtAAFigur e 2: eeprom Component Timing ParametersPC SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 8 of 28 Revision 3: eeprom Data ValiditySDASCLSTARTSTOPSTART = High to low transition of SDA while SCL is highSTOP = Low to high transition of SDA while SCL is highFigure 4: eeprom Start and Stop conditionsSDASCLO utput from transmitterSDAO utput from receiverSTARTACKNOWLEDGE189 ACKNOWLEDGE:Transmitter releases SDA after transmitting eight ninth clock cycle receiver pulls SDA low to acknowledge receit of the eight 5.

7 eeprom AcknowledgePC SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 9 of 28 Revision address(write)STOP word addressdataSYSTEMMASTER: eeprom :SDA1010A2 A1A00 Figure 6: eeprom Byte Write OperationACKACKACKSTART slave address(write)STOP word address (n)data nSYSTEMMASTER: eeprom :SDAdata n+1 ACKACK data n+151010A2A1A00 Figure 7: eeprom Page Write OperationACKSTART slave address (Read)STOP dataSYSTEMMASTER: eeprom :SDA1010A2A1A01 Figure 8: eeprom Current Address Read OperationACKSTART slave address(write)STOP word address nSYSTEMMASTER: eeprom :SDASTART slave address(read)ACKdata nACK1010A2A1A001010A2A1A01 Figure 9: eeprom Random Read OperationPC SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 10 of 28 Revision address(read)STOP data nSYSTEMMASTER: eeprom :SDAACK data n+x1010A2A1A01 ACKdata n+1 ACKF igure 10: eeprom Sequential Read OperationPC SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 11 of 28 Revision Serial Presence Detect eeprom DataTable 5.

8 Serial Presence Detect Data FormatByte NumberFunctionRequired/Optional0 Defines # of bytes written into Serial memory at module manufacturerRequired1 Total # of bytes of SPD memory deviceRequired2 Fundamental memory type (FPM, EDO, ) from Appendix ARequired3# of row addresses on this assembly (includes Mixed-size Row addr)Required4# Column Addresses on this assembly (includes Mixed-size Col addr)Required5# Module Rows on this assemblyRequired6 Data Width of this Data Width continuationRequired8 Voltage interface standard of this assemblyRequired9 SDRAM Cycle time, CL=X (highest CAS latency)Required10 SDRAM Access from Clock (highest CAS latency)Required11 DIMM Configuration type (non-parity, ECC)Required12 Refresh Rate/TypeRequired13 Primary SDRAM WidthRequired14 Error Checking SDRAM widthRequired15 Minimum Clock Delay Back to Back Random Column AddressRequired*16 Burst Lengths SupportedRequired*17# of Banks on Each SDRAM DeviceRequired*18 CAS# Latencies SupportedRequired*19CS# LatencyRequired*20 Write LatencyRequired*21 SDRAM Module AttributesRequired*22 SDRAM Device Attributes.

9 GeneralRequired*23 Min SDRAM Cycle time at CL X-1 (2nd highest CAS latency)Required*24 SDRAM Access from Clock at CL X-1 (2nd highest CAS latency)Required*25 Min SDRAM Cycle time at CL X-2 (3rd highest CAS latency)Optional*26 Max SDRAM Access from Clock at CL X-2 (3nd highest CAS latency)Optional*27 Min Row Precharge Time (Trp)Required*28 Min Row Active to Row Active (Trrd)Required*29 Min RAS to CAS Delay (Trcd)Required*30 Minimum RAS Pulse Width (Tras)Required*31 Density of each row on module (mixed, non-mixed sizes)Required32-61 Superset Information (may be used in future)62 SPD Data Revision CodeRequired63 Checksum for bytes 0-62 Required64-71 Manufacturer s JEDEC ID code per JEP-108 EOptional72 Manufacturing LocationOptional73-90 Manufacturer s Part NumberOptional91-92 Revision CodeOptional93-94 Manufacturing DateOptional95-98 Assembly Serial NumberOptional99-125 Manufacturer Specific DataOptional126 Intel Specification frequencyRequired127 Intel Specification CAS# Latency supportRequired128+Unused storage locationsNotes.

10 Required/Optional* (bold*) are SDRAM only bytesPC SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 12 of 28 Revision 0 - Number of Bytes used by Module Manufacturer (General)This field describes the total number of bytes used by the module manufacturer for the SPD dataand any (optional) specific supplier information. The byte count includes the fields for all requiredand optional of bytesHex 1 - Total SPD Memory Size (General)This field describes the total size of the Serial memory used to hold the Serial Presence Memory SizeHex ValueRFU002 Bytes014 Bytes028 Bytes0316 Bytes0432 Bytes0564 Bytes06128 Bytes07256 Bytes08512 Bytes091024 Bytes0A2048 Bytes0B4096 Bytes0C8192 Bytes0 DByte 2 - Memory Type (General)This field describes the fundamental memory type implemented on the TypeHex SDRAM Serial Presence Detect (SPD) SpecificationDec, 1997 13 of 28 Revision for Bytes 3-4: Bytes 3-4 show a roll-up value for Hex 1, 2, 3 ( , 1row/16rows).