PCB Layout Guideline for Automotive LED Drivers - TI.com

1 1 SNVA766 April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor AutomotiveLEDD riversApplicationReportSNVA766 April2017 PCBL ayoutGuidelinefor AutomotiveLEDD riversSunghoYoonABSTRACTPCB layoutdesignfor automotiveapplicationsrequiresstricterst andardsthanindustrialand personalelectronicsapplicationsfor suchas EMCregulation,operatingtemperatures,and theserequirementsat PCBdesignstageimprovessystemperformancea nd savetheeffortand cost of developmentat purposeof this applicationnoteis to helpuserswithbasicideasaboutPCBdesignfor LEDdriverswith LP8863-Q1 deviceand EVMdesignas examplesand alsoshowsgenericrulesand examplesfor betterPCBdesignwhichcan be providedetailedtheoriesand backgroundsof all Noisy(Switch) (LP8863-Q1).

2 Of Figures1 SimplifiedSchematicof Viewof SW Nodefor Noisy(SW)Nodefor SW LP8863-Q1to GroundLayerfor April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor AutomotiveLEDD rivers16 CapacitorLocationsof for (VIN) of 2017, Texas Instruments LP8863-Q13 SNVA766 April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor AutomotiveLEDD rivers1 TypicalApplicationCircuitof LP8863-Q1 The LP8863-Q1applicationcircuitin Figure1 showsa commonLEDdrivercircuitfor automotiveapplicationswith power-lineFET,currentsenseresistors,indu ctor,boostinput/outputcapacitors,switchi ngFET,diode,capacitorsfor internalchargepump,and host ,an EMI filterwas usedon the LP8863-Q1 EVMto suppresscommonmodenoiseof the SimplifiedSchematicof LP8863-Q1 TypicalApplicationCircuitof April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor AutomotiveLEDD riversFigure2.

3 PCBL ayoutof LP8863-Q1 EVMF igure3. Top Viewof CriticalFactors5 SNVA766 April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor AutomotiveLEDD rivers2 Considerationof CriticalFactorsThe guidelinesin this documentare describedstartingfromthosewith the mostimpactfirst for mostof PCBTI recommends4 or morelayersof PCB,if possible,to isolatenoisynodesfrom/tootherpartsof systemPCBand to shortenGNDpathof eachsignal/powerrail. Use one of the internallayersas a GNDplaneforthis only 2 layersare used,noiseisolationmay not be effective,and the GNDpathcan beunnecessarilylongerthan4 prioritizedbetweencost and layerPCB see stackinformationin Figure4:Figure4. PCBL ayerStackof LP8863-Q1 EVM 1st layer(top): signals/ areasexceptfor signalsand powerrails are coveredwith copperconnectedto GNDto isolatethe traceson it.

4 2nd layer(signallayer1) : GNDplanefor bothdigitaland powerground. 3rd layer(signallayer2) : areasexceptfor signalsare coveredwith copperconnectedto GNDto isolatethe traceson it. 4th layer(Bottom): signals/ areasexceptfor signalsand powerrails arecoveredwith copperconnectedto GNDto isolatethe traceson April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor 2 mainloopsof magneticfield whichcan interfereothercircuitryof strengthof magneticfield is proportionalto loop size;minimizeloop sizeminimized,if and Figure6 show1st and 2nd first loop currentflowsfrominductor,SW FET and to secondloop currentflowsfrominductor,diode,outputcap acitorand to placedas closeas possiblearoundboostcontroller(LEDdriver) and sharesamegroundplaneto reduceloop SwitchingCurrentLoop1 Figure6.

5 CriticalFactors7 SNVA766 April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor AutomotiveLEDD riversFigure7 showsmaincurrentflowsand input,switch,and boostoutputare all centeredand eachcomponenthas enoughvias to connectto groundplanewith CurrentFlowsof April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor switchingFET has DC and AC powerlosseson it. DC loss is causedby the turnonresistanceof theFET,whichis proportionalto can be minimizedby selectinga big enoughFET withlow loss is causedby switchingoperationof the DC-DCconverterand proportionaltoswingvoltage,frequencyand rise/falltime of loss can be a criticalfactorof powerlossespeciallyat high switchingfrequencies,and theremay be a limitationon selectingbig enoughor fastenoughFET to reducethe loss with givenoperatingconditionsdue to the limitationof FET the limitedFET capabilityand natureof DC-DCconverter,thermalaccumulationon switchingFET is.

6 Considerationfor goodthermaldissipationis requiredfor showsthe switchnodeof the switchingFETswereusedto dissipatethepowerloss of CopperAreaof SW Nodefor ThermalDissipationIncreasingswitchnodear eamustbe donecarefullyas it may causea coupleof side Due to big copperarea,parasiticcapacitanceof switchnodeis increased,thus increasingswitchingtime,whichresultsin Largecopperareacan act like an antenna,whichmay ,thereshouldbe sometrade-offfor increasingcopperareaof mostcases,TIrecommendsan areaa few timeslargerthanswitchingthe FET footprintfor high switchingfrequency,suchas a few hundredkHz,the switch-nodeareais not as criticalto AC loss April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor ConnectSwitchCurrentSenseResistorto GroundPlaneSwitchcurrentflowsfromswitchF ET to currentsenseresistorand to pathmustbe largeenoughfor this be calculatedas explainedinSection11.

7 Viacountcan be also calculatedby currentcapacityof eachvia (seeEquation1):Currentcapacity(Aamp)= k Temp_rise( C)bx Area(mils2)cwhere Area= pi (inner_diameter+plating_thickness) plating_thicknessfor IPC-2221externallayers:k = ,b = ,c = ,plating_thickness(min)= 1 mil(1)A via of 8 mil(diameter)was usedon the LP8863-Q1 EVMto connectsenseresistorto the currentcapacityof this via is for a 10 C totalof 12 vias wereusedon the senseresistorgroundof the LP8863-Q1device,whichsupportup to largeenoughfor a maximumswitchingcurrentlimit (approximately10 A). Equation1 can be usedforany otherhigh currentpathsrequiringvia Viasfor GroundPlaneConnectionIsolationof Noisy(Switch) April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor AutomotiveLEDD rivers4 Isolationof Noisy(Switch)NodeEffectiveisolationof noisynodeimprovesEMCcharacteristicsof the DC-DCconvertercan act as an nodewith shortgroundpathseffectivelyisolatesthe noiseby removingcouplingto othercircuitsand localizeit showsthat switchingnodeis surroundedby polygonconnectedto groundlayerswith viasfor Isolationof Noisy(SW)Nodefor EMCI mprovementFigure11.

8 LocalizingNoiseSourceto Gate-DriveSignal11 SNVA766 April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor AutomotiveLEDD rivers5 Traceof Gate-DriveSignalThe traceof gatedrivesignalfor switchingFET mustbe shortand wideto reduceinductanceandresistanceto avoidringingand is one of the mostcriticaltracesfor Gate-DriveSignalFromLP8863-Q1to SW FET6 LEDD river(LP8863-Q1)LEDdriveritselfcan havepowerloss by headroomvoltageof thereare high voltagemismatchesof total Vfof eachLEDstring,the LEDdriverinputswith high headroomvoltage(thatis, theLEDstringwith lowesttotal Vf) has high orderto avoidexcessivethermalaccumulationonthe LEDdriver,its die-attachpad (DAP)mustconnectedto GNDplanewith manyvias LP8863-Q1 EVMuses12 20-mil(outerdiameter)vias to connectDAPof the deviceto ViasfromDAPof LP8863-Q1to GroundLayerfor April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor AutomotiveLEDD riversAddingvias on the DAPhelpsreducedie temperatureand makesenoughcurrentpathfor LEDdriver(DAPof LP8863-Q1is LEDground).

9 Thermalimpedanceof eachvia usedon LP8863-Q1 EVBisestimatedas approximately26 C/W(seeEquation2), so use as manyvias as requiredfor expectedpowerdissipationon LEDdriverand temperaturerequirement. cu-via= L / (K x (D02 D12) / 4where L = lengthof via K = thermalconductivityof copper(9W/in C) D0= outerdiameterof via(20mil) D1= Innerdiameterof via(8mil)(2)7 LogicPowerInputThe logicpowerinputof LEDdrivermay containnoisesor ripples,whichcan disturbdigital(or evenanalog)operationof noisesor ripplesbeforelogicpoweris inputtedto few F (for example, F) of capacitanceis usedas a low-passfilter,and thesecapacitorsmustbe placedat nearestpointto the BypassCapacitorsof BoostFeedbackSignal13 SNVA766 April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor AutomotiveLEDD rivers8 Traceof BoostFeedbackSignalThe feedbacksignalof boostoutputis returnedto LEDdriver(LP8863-Q1))

10 For isolatedor not affectedfromexternalnoiseor crosstalkfromneighboringsignalssothat the stableboostcontrolis not shownin Figure15, feedbacktraceis isolatedfromboost-switchnodeby groundpolygonand vias (to groundlayer)on the top layerand buriedin the innerlayerwheregroundlayeris in Tracefor April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor AutomotiveLEDD rivers9 ChargePumpThe LP8863-Q1has an internalchargepumpto doublethe gate-drivevoltageof switchFET fromexternallow at least2 capacitorsfor is flyingcapacitorforchargepumpswitching,an d anotherone is the nearestlocationfromthecharge-pumpcontrol ler(LP8863-Q1)to avoidunnecessarynoiseand ringingby tracewidthof flyingcapacitorand outputcapacitormustbe able to handlemaximumdrivingcurrentof chargepumpnot causingexcessivevoltagedropand CapacitorLocationsof April2017 SubmitDocumentationFeedbackCopyright 2017,TexasInstrumentsIncorporatedPCBL ayoutGuidelinefor AutomotiveLEDD rivers10 Power-LineFETA power-lineFET may or may not be usedfor this FET is not used,tracewidthmustcalculatedto be wideenoughto flow the currentwithoutexcessivetemperatureincrea se,whichisdiscussedSection11.