PCI Expressの概要 - Oscilloscopes

1 Copyright Lattice Semiconductor 2007 Slide Ref -1 PCI Express Copyright Lattice Semiconductor 2007 Slide Ref -2 PCI PCI Express FSBC hipsetChipsetCPUCPUV ideoAGPSDRSDRAMHardDriveIDEPCIFSBC hipsetChipsetCPUCPUV ideox16 PCI ExpressDDR1/2 SDRAMHardDriveSATAx1, x4, x8 PCI ExpressPCI BasedPCI Express BasedCardSlotsCardSlots 1 2 ( ) Peer to Peer ( )Copyright Lattice Semiconductor 2007 Slide Ref -3 PCI PCI Express PCI Express PCI Copyright Lattice Semiconductor 2007 Slide Ref -4 PCI PCI Express PCI C/BE PCI Express PCIPCI ExpressCopyright Lattice Semiconductor 2007 Slide Ref -5 PCI Express PCI PCI PCI Express PHY Lattice FPGA PCI Express Copyright Lattice Semiconductor 2007 Slide Ref -6 PCI CPU Copyright Lattice Semiconductor 2007 Slide Ref -7 PCI/PCI-X PCI PCI-X

2 PCI-X266/533 DDR/QDR PCI-X533 Burst Write TransactionCopyright Lattice Semiconductor 2007 Slide Ref -8 PCI/PCI-X 1 Setup/Hold-time 2 Copyright Lattice Semiconductor 2007 Slide Ref -9 PCI Express I/O (Gen1) (full Duplex) PCI(64bit 66 MHz) 32 CDR(Clock Data Recovery) Setup/Hold-time 20ns PCI(64bit 66 MHz) : 64 ( ) PCI Express x1 : 4 PCI Express Copyright Lattice Semiconductor 2007 Slide Ref -10.

3 Copyright Lattice Semiconductor 2007 Slide Ref -11 PCI PCI Express / Lattice FPGA LUT PCI Target(64bit 66 MHz) 569 1219 PCI Express x137275631 PHY / SERDES Copyright Lattice Semiconductor 2007 Slide Ref -12 PCI Express PCI PCI PCI Express PHY Lattice FPGA PCI Express Copyright Lattice Semiconductor 2007 Slide Ref -13 PCI Express PCI Copyright Lattice Semiconductor 2007 Slide Ref -14 PCI Express I/O PCI PCI Express (PCI Express )Copyright Lattice Semiconductor 2007 Slide Ref -15 PCI Express TLP(Transaction Leyer Packet)

4 ( ) ( ) VC0VC1VC7 TLPTLP Headder Copyright Lattice Semiconductor 2007 Slide Ref -16 PCI Express LCRC PHY PHY LCRC ACK/NAK PHY ACK : NAK : Copyright Lattice Semiconductor 2007 Slide Ref -17 PCI Express PHY PHY SERDES -- ( ) 32 1 -- x1/x2/../x32 -- Logical Electorical 2 Copyright Lattice Semiconductor 2007 Slide Ref -18 PHY SERDES PHY PHY PIPE PIPE InterfaceMACP hysical Coding Sublayer(PCS)Physical Media Attachment Layer (PMA)

5 TxRxChannelLogical Electorical PIPEPHY Interface For The PCI Express ArchitectureCopyright Lattice Semiconductor 2007 Slide Ref -19 PCI Express Copyright Lattice Semiconductor 2007 Slide Ref -20 PCI Express PCI PCI PCI Express PHY Lattice FPGA PCI Express Copyright Lattice Semiconductor 2007 Slide Ref -21 PHY PHY 2 Logical / 8B10B / Electrical ( 300ppm) AC / ESD & ( )Copyright Lattice Semiconductor 2007 Slide Ref -22 Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0 Byte8 Byte4 Byte0 Byte9 Byte5 Byte1 Byte10 Byte6 Byte2 Byte11 Byte7 Byte3x4 Lane0 ScramblerLane1 ScramblerLane2 ScramblerLane3 ScramblerCopyright Lattice Semiconductor 2007 Slide Ref -23 / PCI Express Base Spacification LFSR(Linear Feedback Shift Register) XOR K (SKIP/TS1/TS2 ) Copyright Lattice Semiconductor 2007 Slide Ref -24 / ?

6 EMI(Erectro Magnetic Interference : ) : 0 1 8B10B 0/1 Copyright Lattice Semiconductor 2007 Slide Ref -258B10B / 8bit 10bit 8B10B 6bit RD(Running Disparity)+/- 0/1 0/1 (DC ) B10B Copyright Lattice Semiconductor 2007 Slide Ref -268B10B ? SERDES 0 1 2 Jitter (Data Depentent Jitter) 3 1 (10bit) 8B10B (K ) Copyright Lattice Semiconductor 2007 Slide Ref -27 1180 1538 (byte) 1 SKIP SKIP 300ppm COMSKPSKPSKPSKIP 4byteCopyright Lattice Semiconductor 2007 Slide Ref -28 Packet0 COMP acket1 SKPSKPSKPSERDES ( )Packet0 COMP acket1 SKPSKPSKP SKP ( )

7 Packet0 COMP acket1 SKPSKPSKIP : 4byteSERDESRx (FIFO)etc ( )Copyright Lattice Semiconductor 2007 Slide Ref -29 Tx (TS1/TS2) CDR (Gen1 : , Gen2 : ) Copyright Lattice Semiconductor 2007 Slide Ref -30 PCI Express TS Copyright Lattice Semiconductor 2007 Slide Ref -31 (1) (Gen1/2) Gen2 TS1 6 15 8B10B ( ) Normal Reverse+--+++--Copyright Lattice Semiconductor 2007 Slide Ref -32 (2)

8 PCI Express / Lane0 Lane1 Lane2 Lane3 Lane3 Lane2 Lane1 Lane0x4 Lane ReverseCopyright Lattice Semiconductor 2007 Slide Ref -33 (3) COM( ) Lane0 RxTS1/TS2 Lane1 RxLane2 RxLane3 RxDelayDelayDelayDelayCOMTS1/TS2 COMTS1/TS2 COMTS1/TS2 COMTS1/TS2 COMCOMCOMCOMTS1/TS2TS1/TS2TS1/TS2 Copyright Lattice Semiconductor 2007 Slide Ref -34 ? PCI Express Copyright Lattice Semiconductor 2007 Slide Ref -35 PLL (100 MHz.)

9 ClockPhase1 clock Phase7 clock1/8 ( ) 100 MHz PLL 25 8 Copyright Lattice Semiconductor 2007 Slide Ref -36AC 75 200nF / DC Copyright Lattice Semiconductor 2007 Slide Ref -37 AC Ctx AC Ctx Copyright Lattice Semiconductor 2007 Slide Ref -38 2bit 2bit ( ) Copyright Lattice Semiconductor 2007 Slide Ref -39 1/ 11/ 00/ 10/ 0jitter 1UI Copyright Lattice Semiconductor 2007 Slide Ref -40 PCI Express PCI PCI PCI Express PHY Lattice FPGA PCI Express Copyright Lattice Semiconductor 2007 Slide Ref -41 LatticeECP2M LUT FPGA 19K 95K LUT4 144 601 I/O sysIOTM LVCMOS 33/25/18/15/12, PCI SSTL3/2/18 HSTL15 HSTL18 Bus-LVDS, MLVDS.

10 LVPECL & LVDS sysDSPTM 24 168 18x18 sysMEMTM sysCLOCKTMPLL DLL SPI SERDES 16 channels 270 Mbps Copyright Lattice Semiconductor 2007 Slide Ref -42 ECP2M1156-ball fpBGA (35x35mm)16/601355070201924416612178/2 SERDES/IO4/1444/301674834327111421018/24 /3014/411968810122541478/24/2878/3871452 4645348/28/45716/449 100 LUT (K) 9518x18 (Kbits)202168 EBR 288 EBR (Kbits)5308 PLL / DLL 8/2 256-ball fpBGA (17x17mm)672-ball fpBGA (27x27mm)484-ball fpBGA (23x23mm)900-ball fpBGA (31x31mm)16/457 LatticeECP2M Copyright Lattice Semiconductor 2007 Slide Ref -43 LatticeECP2M SERDES Jitter (PRBS 27-1 ) Tx Jitter : (Typical @ Gbps) Rx Jitter : (Typical @ ) 90mW (Typical @ ) ( ) 4 (0%, 16%, 32%, 48%) 3 (short, medium, long) Copyright Lattice Semiconductor 2007 Slide Ref -44 PCS PCI Express PHY / 8B10B / (SKIP )Copyright Lattice Semiconductor 2007 Slide Ref -45.