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PD - 9.1478A IRF4905S/L - Infineon Technologies

irf4905s /LHEXFET Power MOSFETPD - Process TechnologylSurface Mount ( irf4905s )lLow-profile through-hole (IRF4905L)l175 C Operating TemperaturelFast SwitchinglP-ChannellFully Avalanche Rated8/25/97 SDGA bsolute Maximum RatingsFifth Generation HEXFETs from International Rectifierutilize advanced processing techniques to achieveextremely low on-resistance per silicon area. Thisbenefit, combined with the fast switching speed andruggedized device design that HEXFET Power MOSFET sare well known for, provides the designer with an extremelyefficient and reliable device for use in a wide variety D2 Pak is a surface mount power package capable ofaccommodating die sizes up to HEX-4. It provides thehighest power capability and the lowest possible on-resistance in any existing surface mount package. TheD2 Pak is suitable for high current applications because ofits low internal connection resistance and can dissipateup to in a typical surface mount through-hole version (IRF4905L) is available for low-profile = -55 VRDS(on) = ID = -74A2 D Pa k JCJunction-to-Case JAJunction-to-Ambient ( PCB Mounted,steady-state)** 40 Thermal Resistance @ TC = 25 CContinuous Drain Current, VGS @ -10V -74ID @ TC = 100 CContinuous Drain Current, VGS @ -10V -52 AIDMP ulsed Drain Current -260PD @TA = 25 CPower @TC = 25 CPower Diss

IRF4905S/L Fig 4. Normalized On-Resistance Vs. Temperature Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics …

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Transcription of PD - 9.1478A IRF4905S/L - Infineon Technologies

1 irf4905s /LHEXFET Power MOSFETPD - Process TechnologylSurface Mount ( irf4905s )lLow-profile through-hole (IRF4905L)l175 C Operating TemperaturelFast SwitchinglP-ChannellFully Avalanche Rated8/25/97 SDGA bsolute Maximum RatingsFifth Generation HEXFETs from International Rectifierutilize advanced processing techniques to achieveextremely low on-resistance per silicon area. Thisbenefit, combined with the fast switching speed andruggedized device design that HEXFET Power MOSFET sare well known for, provides the designer with an extremelyefficient and reliable device for use in a wide variety D2 Pak is a surface mount power package capable ofaccommodating die sizes up to HEX-4. It provides thehighest power capability and the lowest possible on-resistance in any existing surface mount package. TheD2 Pak is suitable for high current applications because ofits low internal connection resistance and can dissipateup to in a typical surface mount through-hole version (IRF4905L) is available for low-profile = -55 VRDS(on) = ID = -74A2 D Pa k JCJunction-to-Case JAJunction-to-Ambient ( PCB Mounted,steady-state)** 40 Thermal Resistance @ TC = 25 CContinuous Drain Current, VGS @ -10V -74ID @ TC = 100 CContinuous Drain Current, VGS @ -10V -52 AIDMP ulsed Drain Current -260PD @TA = 25 CPower @TC = 25 CPower Dissipation200 WLinear Derating CVGSGate-to-Source Voltage 20 VEASS ingle Pulse Avalanche Energy 930mJIARA valanche Current -38 AEARR epetitive Avalanche Energy 20mJdv/dtPeak Diode Recovery dv/dt Junction and-55 to + 175 TSTGS torage Temperature RangeSoldering Temperature, for 10 seconds300 ( from case )

2 CIRF4905S/L Starting TJ = 25 C, L = RG = 25 , IAS = -38A. (See Figure 12) Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 )Notes:** When mounted on 1" square PCB (FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. ISD -38A, di/dt -270A/ s, VDD V(BR)DSS, TJ 175 C Pulse width 300 s; duty cycle 2%. Uses IRF4905 data and test conditionsSource-Drain Ratings and ConditionsV(BR)DSSD rain-to-Source Breakdown Voltage-55 VVGS = 0V, ID = -250 A V(BR)DSS/ TJBreakdown Voltage Temp. Coefficient V/ CReference to 25 C, ID = -1mA RDS(on)Static Drain-to-Source On-Resistance VGS = -10V, ID = -38A VGS(th)Gate Threshold = VGS, ID = -250 AgfsForward Transconductance21 SVDS = -25V, ID = -38A -25 AVDS = -55V, VGS = 0V -250 VDS = -44V, VGS = 0V, TJ = 150 CGate-to-Source Forward Leakage 100 VGS = 20 VGate-to-Source Reverse Leakage -100nAVGS = -20 VQgTotal Gate Charge 180ID = -38 AQgsGate-to-Source Charge 32nCVDS = -44 VQgdGate-to-Drain ("Miller") Charge 86 VGS = -10V, See Fig.

3 6 and 13 td(on)Turn-On Delay Time 18 VDD = -28 VtrRise Time 99 ID = -38 Atd(off)Turn-Off Delay Time 61 RG = tfFall Time 96 RD = , See Fig. 10 Between lead, and center of die contactCissInput Capacitance 3400 VGS = 0 VCossOutput Capacitance 1400 pFVDS = -25 VCrssReverse Transfer Capacitance 640 = , See Fig. 5 Electrical Characteristics @ TJ = 25 C (unless otherwise specified)IGSSnsIDSSD rain-to-Source Leakage Source Inductance ConditionsISContinuous Source CurrentMOSFET symbol(Body Diode) showing theISMP ulsed Source Currentintegral reverse(Body Diode) p-n junction Forward Voltage = 25 C, IS = -38A, VGS = 0V trrReverse Recovery Time 89130nsTJ = 25 C, IF = -38 AQrrReverse Recovery Charge 230350nCdi/dt = -100A/ s tonForward Turn-On TimeIntrinsic turn-on time is negligible (turn-on is dominated by LS+LD)ASDG-74-260 irf4905s /LFig 4.

4 Normalized On-ResistanceVs. TemperatureFig 2. Typical Output CharacteristicsFig 1. Typical Output CharacteristicsFig 3. Typical Transfer 20 s PULSE WIDTH T = 25 CcA-I , D rain-to-Source C urrent (A)-V , Drain-to-Source Voltage (V) VGS TOP - 15V - 10V - - - - - BO TT OM - 4. 5V , Drain-to-Source Current (A)-V , Drain-to-Source Voltage (V) VGS TOP - 15V - 10V - - - - - BO TT OM - 4. V 20 s PULSE WIDTH T = 175 CC110100100045678910T = 25 CJGSDA-I , D rain -to-Source C urrent (A)-V , Ga te-to-So urce Voltage (V) V = -2 5 V 20 s PULSE W IDTH DST = 175 -40 -20020406080100 120 140 160 180JT , Junction Temperature ( C)R , D rain -to -S ourc e O n R e sistan ceDS(on)(Norm alized)A V = -10 V GS I = -64 ADTJ = 25 CTJ = 175 CIRF4905S/LFig 8.

5 Maximum Safe Operating AreaFig 6. Typical Gate Charge Vs. Gate-to-Source VoltageFig 5. Typical Capacitance Vs. Drain-to-Source VoltageFig 7. Typical Source-Drain DiodeForward Voltage010002000300040005000600070001101 00C, Capacitance (pF)ADS-V , Drain-to-Source Voltage (V)V = 0 V, f = 1M H zC = C + C , C SH O RTE DC = CC = C + CGSiss gs gd dsrss gdo ss ds g dC is sC ossC rs s04812162004080120160200 GGSA-V , G ate-to-S ource V oltage (V )Q , Total G ate C harge (nC) FOR TEST CIRCUIT SEE FIGURE 13 I = -38A V = - 44V V = - = 25 CJV = 0 V GSSDSDA-I , R eve rse D ra in Current (A)-V , Source-to-Drain Voltage (V)T = 175 CJ1101001000110100 OPE R ATIO N IN TH IS A RE A LIMITE D BY RDS(on)10m sA-I , D rain C urre nt (A)-V , Drain-to-Source Voltage (V)DSD100 s1m s T = 2 5 C T = 1 75 C Single PulseCJIRF4905S/LFig 10a.

6 Switching Time Test CircuitFig 10b. Switching Time WaveformsFig 11. Maximum Effective Transient Thermal Impedance, Junction-to-CaseFig 9. Maximum Drain Current TemperatureVDS-10 VPulse Width 1 sDuty Factor % +-VDS90%10%VGStd(on)trtd(off)tf255075100 125150175020406080T , Case Temperature( C)I , Drain Current (A) 1 Notes:1. Duty factor D =t / t2. Peak T=Px Z+ T12 JDMthJCCPttDM12t , Rectangular Pulse Duration (sec)Thermal Response(Z ) = PULSE(THERMAL RESPONSE) irf4905s /LFig 13b. Gate Charge Test CircuitFig 13a. Basic Gate Charge WaveformFig 12c. Maximum Avalanche EnergyVs. Drain F50K .2 F12 VCurrent RegulatorSame Type as Sampling Resistors+-Fig 12b. Unclamped Inductive WaveformsFig 12a. Unclamped Inductive Test CircuittpV(BR) , S ingle Pulse Avalanche E nergy (m J)ASAS tarting T , Junction Temperature ( C) ITO P -1 6A - 27 ABOT TO M -38 ADIRF4905S/LPeak Diode Recovery dv/dt Test Recoverydv/dtRipple 5%Body Diode Forward DropRe-AppliedVoltageReverseRecoveryCurr entBody Diode ForwardCurrentVGS=10 VVDDISDD river Gate VDSW aveformInductor CurentD = P.

7 W .Period+-+++--- RGVDD dv/dt controlled by RG ISD controlled by Duty Factor "D" - Device Under *Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer * Reverse Polarity of for P-ChannelVGS[ ][ ]** VGS = for Logic Level and 3V Drive Devices[ ] **Fig 14. For P-Channel HEXFETSIRF4905S/LD2 Pak Package OutlineD2 PakPart Marking (.400) R E F . (.255) (.243) (.103) (.091) (.350) R E B (.052) (.048) (.110) (.090) (.055) (.045) (.208) (.188) (.185) (.165) (.415) (.405)- A -21 (.610) (.580) (.037) (.027) (.200) (.055) (.045) (.070) (.050) (.055) : 1 DIMENSIONS AFTER SOLDER DIP. 2 DIM ENSIONING & TOLERANCING PER ANSI , 1982. 3 CONTROLLING DIMENSION : INCH. 4 HEATSINK & LEAD DIMEN SION S DO NOT INCLUDE (.022) (.018) (.)

8 010) M B A MMINIMUM RECOMMENDED (.450) (.350) (.700) (.150) (.082) 2 XLE AD ASS IGNM ENTS 1 - G AT E 2 - D R A IN 3 - S OU RC (.100) 2 XPART NUMBERIN TER N ATIO N AL REC TIFIER LOGODATE CODE (YYWW )YY = YEARWW = WEEK ASSEMBLY LOT CODEF530S9B 1M9246 AIRF4905S/LPackage OutlineTO-262 OutlineTO-262 Part Marking InformationIRF4905S/LTape & Reel InformationD2 PakWORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 and specifications subject to change without (.

9 073) (.065) (.063) (.059) (.161) (.153)TRLFEED (.429) (.421) (.634) (.626) (.0 69 ) (.0 49 )11 .6 0 (.45 7 )11 .4 0 (.44 9 )15 .4 2 (.60 9 )15 .2 2 (.60 1 ) (.136) (.178) (.957) (.941) (.0145) (.0135) (.063) (.059)1 0 (.532 )1 0 (.504 )33 0( 3) M AX .2 0 (1 .079 )2 0 (.9 41)6 0 (2 .36 2) M IN .3 0 (1 .19 7) M A X .26 .40 ( 9) (.961)NOT ES :1. CO MFO R MS TO EIA -418 .2. CO NTRO LLIN G DIM EN SION : M ILLIM ETER .3. DIM ENSIO N M EASURED @ INCLUDES FLANGE DISTORTION @ OUTER : For the most current drawings please refer to the IR website at.


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