PHY Interface for PCI Express*, SATA, and USB 3.1: …

1 PHY Interface For the PCI Express, SATA, USB , DisplayPort, and Converged IO Architectures Version 2007 - 2018 Intel Corporation All rights reserved. PHY Interface for PCI Express, SATA, USB , DisplayPort, and Converged IO Architectures, ver 2007-2018 Intel Corporation All rights reserved Page 2 of 161 Intellectual Property Disclaimer THIS SPECIFICATION IS PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE.

2 A COPYRIGHT LICENSE IS HEREBY GRANTED TO REPRODUCE AND DISTRIBUTE THIS SPECIFICATION FOR INTERNAL USE ONLY. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY OTHER INTELLECTUAL PROPERTY RIGHTS IS GRANTED OR INTENDED HEREBY. INTEL CORPORATION AND THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF PROPRIETARY RIGHTS, RELATING TO IMPLEMENTATION OF INFORMATION IN THIS DOCUMENT AND THE SPECIFICATION. INTEL CORPORATION AND THE AUTHORS OF THIS SPECIFICATION ALSO DO NOT WARRANT OR REPRESENT THAT SUCH IMPLEMENTATION(S) WILL NOT INFRINGE SUCH RIGHTS. ALL SUGGESTIONS OR FEEDBACK RELATED TO THIS SPECIFICATION BECOME THE PROPERTY OF INTEL CORPORATION UPON SUBMISSION.

3 INTEL CORPORATION MAY MAKE CHANGES TO SPECIFICATIONS, PRODUCT DESCRIPTIONS, AND PLANS AT ANY TIME, WITHOUT NOTICE. Notice: Implementations developed using the information provided in this specification may infringe the patent rights of various parties including the parties involved in the development of this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights (including without limitation rights under any party s patents) are granted herein. All product names are trademarks, registered trademarks, or service marks of their respective owners Contributors Jeff Morris Jim Choate Michelle Jen Kaleb Ruof Andy Martwick Paul Mattos Bruce Tennant John Watkins Brad Hosler Dan Froelich Quinn Devine Jamie Johnston Matthew Myers Duane Quiet Su Wei Lim Todd Witter Bob Dunstan Hajime Nozaki Hooi Kar Loo Andrea Uguagliati Saleem Mohammad Peter Teng Poh Thiam Teoh Efraim Kugman Sue Vining Karthi Vadivelu Sathyanarayanan Gopal Daniel Resnick Tadashi Iwasaki Mineru Nishizawa Siang Lin Tan Tina Tahmoureszadeh Yoichi Iizuka Takanori Saeki Jake Li Rahman Ismail Ben Graniello Andrew Lillie Frank Kavanagh Zeeshan Sarwar Minxi Gao

4 PHY Interface for PCI Express, SATA, USB , DisplayPort, and Converged IO Architectures, ver 2007-2018 Intel Corporation All rights reserved Page 3 of 161 Dedicated to the memory of Brad Hosler, the impact of whose accomplishments made the Universal Serial Bus one of the most successful technology innovations of the Personal Computer era. PHY Interface for PCI Express, SATA, USB , DisplayPort, and Converged IO Architectures, ver 2007-2018 Intel Corporation All rights reserved Page 4 of 161 Table of Contents 1 Preface .. 10 Scope of this Revision .. 10 Revision History .. 10 2 Introduction.

5 13 PCI Express PHY Layer .. 16 USB PHY Layer .. 17 Converged IO PHY Layer .. 17 SATA PHY Layer .. 17 Low Pin Count Interface and SerDes Architecture .. 18 3 PHY/MAC Interface .. 19 4 PCI Express, USB, and Converged IO PHY Functionality .. 28 Original PIPE Architecture .. 28 Transmitter Block Diagram ( and GT/s) .. 28 Transmitter Block Diagram ( GT/s/32 GT/s) .. 29 Receiver Block Diagram ( and GT/s) .. 29 Receiver Block Diagram ( GT/s) .. 30 Clocking .. 32 SerDes Architecture .. 32 SerDes Architecture: Transmitter Block Diagram .. 32 SerDes Architecture: Receiver Block Diagram .. 33 5 SATA PHY Functionality.

6 34 Transmitter Block Diagram ( , , and GT/s) .. 35 Receiver Block Diagram ( , and GT/s) .. 36 Clocking .. 36 6 PIPE Interface Signal Descriptions .. 37 PHY/MAC Interface Signals Common for SerDes and Original PIPE .. 37 Data Interface .. 37 Command Interface .. 40 Status Interface .. 57 Message Bus Interface .. 64 Message Bus Interface Commands .. 64 Message Bus Interface Framing .. 67 PHY/MAC Interface Signals SerDes Architecture Only .. 68 Data Interface .. 68 Command Interface .. 68 PHY/MAC Interface Signals Original PIPE Only .. 69 Data Interface .. 69 Command Interface .

7 72 External Signals Common for SerDes and Original PIPE .. 77 7 PIPE Message Bus Address Spaces .. 80 PHY Registers .. 82 Address 0h: RX Margin Control0 .. 83 Address 1h: RX Margin Control1 .. 83 Address 2h: Elastic Buffer Control .. 83 Address 3h: PHY RX Control0 .. 84 Address 4h: PHY RX Control1 .. 85 Address 5h: PHY RX Control2 .. 85 Address 6h: PHY RX Control3 .. 85 Address 7h: Elastic Buffer Location Update Frequency .. 86 PHY Interface for PCI Express, SATA, USB , DisplayPort, and Converged IO Architectures, ver 2007-2018 Intel Corporation All rights reserved Page 5 of 161 Address 8h: PHY RX Control4.

8 86 Address 400h: PHY TX Control0 .. 87 Address 401h: PHY TX Control1 .. 87 Address 402h: PHY TX Control2 .. 88 Address 403h: PHY TX Control3 .. 89 Address 404h: PHY TX Control4 .. 89 Address 405h: PHY TX Control5 .. 89 Address 406h: PHY TX Control6 .. 90 Address 407h: PHY TX Control7 .. 91 Address 408h: PHY TX Control8 .. 91 Address 409h: PHY TX Control9 .. 92 Address 800h: PHY Common Control0 .. 92 MAC 93 Address 0h: RX Margin Status0 .. 94 Address 1h: RX Margin Status1 .. 95 Address 2h: RX Margin Status2 .. 95 Address 3h: Elastic Buffer Status .. 96 Address 4h: Elastic Buffer Location.

9 96 Address 5h: Reserved .. 96 Address 6h: RX Status0 .. 96 Address 7h: RX Status1 .. 97 Address 8h: RX Status2 .. 97 Address 9h: RX Status3 .. 97 Address Ah: RX Link Evaluation Status0 .. 97 Address Bh: RX Link Evaluation Status1 .. 98 Address Ch: RX Status4 .. 99 Address Dh: RX Status5 .. 99 Address 400h: TX Status0 .. 99 Address 401h: TX Status1 .. 100 Address 402h: TX Status2 .. 100 Address 403h: TX Status3 .. 100 Address 404h: TX Status4 .. 100 Address 405h: TX Status5 .. 101 Address 406h: TX Status6 .. 101 8 PIPE Operational Behavior .. 101 Clocking .. 101 Clocking Topologies.

10 102 Reset .. 104 Power Management PCI Express Mode .. 105 Power Management USB Mode .. 107 Power Management SATA Mode .. 109 Changing Signaling Rate, PCLK Rate, or Data Bus Width .. 110 PCI Express Mode .. 110 USB Mode .. 111 SATA Mode .. 111 Fixed data path implementations .. 112 Fixed PCLK implementations .. 113 Transmitter Margining PCI Express Mode and USB Mode .. 113 Selectable De-emphasis PCI Express Mode .. 114 Receiver Detection PCI Express Mode and USB Mode .. 114 Transmitting a beacon PCI Express Mode .. 115 PHY Interface for PCI Express, SATA, USB , DisplayPort, and Converged IO Architectures, ver 2007-2018 Intel Corporation All rights reserved Page 6 of 161 Transmitting LFPS USB Mode.