Example: dental hygienist

Physics of Advanced CMOS VLSI Dennis Buss Texas ...

Dennis BussTexas instruments , , Texas USAP hysics of Advanced cmos VLSIP hysics of Advanced cmos VLSIC onclusions For the past 35 years, transistors have been developed using Electrical Engineering Physics , which was codified in the early 60 s As the industry approaches the End of Roadmap , Electrical Engineering Physics is no longer sufficient. Technology development increasingly requires Sophisticated quantum Physics Non-equilibrium Boltzmann transport Material science at the atomic and electron orbital level This has implications for Physics education Career opportunities for physicists in the semiconductor industry For the past 35 years, transistors have been developed using Electrical Engineering Physics , which was codified in the early 60 s As the industry approaches the End of Roadmap , Electrical Engineering Physics is no longer sufficient. Technology development increasingly requires Sophisticated quantum Physics Non-equilibrium Boltzmann transport Material science at the atomic and electron orbital level This has implications for Physics education Career opportunities for physicists in the semiconductor industryAgenda Introduction to cmos vlsi Technology Physics challenges to continued vlsi scaling Conclusion Introduction to cmos vlsi Technology Physics challenges to continued vlsi scaling ConclusionUS Patent # 3,138,743 Filed Feb.

Dennis Buss Texas Instruments, Inc. Dallas, Texas USA Physics of Advanced CMOS VLSI. Conclusions ... Introduction to CMOS VLSI Technology ... Scaling CMOS to the “End of Roadmap” will require sophisticated condensed matter physics.

Fullscreen Download

Tags:

  Texas, Instruments, Subs, Dallas, Cmos, Vlsi, Cmos vlsi, Buss texas instruments

Information

Domain:

Source:

Link to this page:

Please notify us if you found a problem with this document:

Other abuse

Transcription of Physics of Advanced CMOS VLSI Dennis Buss Texas ...

1 Dennis BussTexas instruments , , Texas USAP hysics of Advanced cmos VLSIP hysics of Advanced cmos VLSIC onclusions For the past 35 years, transistors have been developed using Electrical Engineering Physics , which was codified in the early 60 s As the industry approaches the End of Roadmap , Electrical Engineering Physics is no longer sufficient. Technology development increasingly requires Sophisticated quantum Physics Non-equilibrium Boltzmann transport Material science at the atomic and electron orbital level This has implications for Physics education Career opportunities for physicists in the semiconductor industry For the past 35 years, transistors have been developed using Electrical Engineering Physics , which was codified in the early 60 s As the industry approaches the End of Roadmap , Electrical Engineering Physics is no longer sufficient. Technology development increasingly requires Sophisticated quantum Physics Non-equilibrium Boltzmann transport Material science at the atomic and electron orbital level This has implications for Physics education Career opportunities for physicists in the semiconductor industryAgenda Introduction to cmos vlsi Technology Physics challenges to continued vlsi scaling Conclusion Introduction to cmos vlsi Technology Physics challenges to continued vlsi scaling ConclusionUS Patent # 3,138,743 Filed Feb.

2 6, 1959 Integrated Circuit 1958 SiO21200 AGate LengthOxide ThicknessGate MaterialJunction DepthInterconnectMask LevelsGate LengthOxide ThicknessGate MaterialJunction DepthInterconnectMask LevelsMOS ScalingLate 60'sLate 60'sLate 60's2000200010 m120 mAl510 m120 mAl5120 nm12 Apoly-Si25/70 nmCu25 - 35120 nm12 Apoly-Si25/70 nmCu25 - 35 Metal Gate10 m1200 mModern CMOSM odern CMOSB eginning ofSubmicron CMOSB eginning ofSubmicron CMOSDeep UV LithoDeep UV Litho90 nm in 200490 nm in 2004 Presumed Limitto ScalingPresumed Limitto ScalingMoore's Law10 um1 um100 nm10 nm1 nm19701980199020002010202034 Years of Scaling History Every generation Feature size shrinks by 70% Transistor density doubles Wafer cost increases by 20% Chip cost comes down by 40% Generations occur regularly On average every years over the past 34 years Recently every 2 yearsFeature SizeTransistor DensityChip SizeTransistors/ChipClock FrequencyPower DissipationFab CostWW

3 IC RevenueWW Electronics RevenueFeature SizeTransistor DensityChip SizeTransistors/ChipClock FrequencyPower DissipationFab CostWW IC RevenueWW Electronics Revenue19701970 TodayToday6 um~10 mm21000100 kHz~100 mW~$10 M$700 M$70 B6 um~10 mm21000100 kHz~100 mW~$10 M$700 M$70 BChangeChange34 Years of History90 nm~400 mm2200 M> 1 GHz~100 W>$1 B$170 B$ T90 nm~400 mm2200 M> 1 GHz~100 W>$1 B$170 B$ T70x Reduction5000x Increase40x Increase200,000x Increase>10,000x Increase~1000x Increase>100x Increase240x Increase16x Increase70x Reduction5000x Increase40x Increase200,000x Increase>10,000x Increase~1000x Increase>100x Increase240x Increase16x IncreaseElectrical Engineering Physicsf(E) = f(E) = 1e(E - E )/kT + 1Fp = Nv e (F -E )/kTp = Nv e (F -E )/kTpv= = ( p - n + Nd-Na ) = = ( p - n + Nd-Na ) d2V(x)dx2+ (x) q-n = Nc e (E -F )/kTn = Nc e (E -F )/kTcnJn(x) = q nn(x) (x) + qDnJn(x) = q nn(x) (x) + qDndn(x)dxJp(x) = q p p(x) (x) - qDpJp(x) = q p p(x) (x) - qDpdp(x)dxEgElectronMassValenceBandCondu ctionBandHoleMass High Performance Processor@ 90nm 256 million transistors 37nm gate length PNO gate: 10 nm EOT NiSi2/Poly gate 8 levels Cu with low-k interlevel dielectric 0204060801002004200620082010201220142015 Heading for ChangeGate Length (nm)Heading for ChangeGate Length (nm)020406080100200420062008201020122014 2015 ChallengesChallenges Push cmos as far as we can (to "end of roadmap") Invent next generation electronics Push cmos as far as we can (to "end of roadmap") Invent next generation electronicsLithographyYear of ProductionResolution ( m)Lithography will not ultimately limit IC feature size!

4 = 436nmi-line = 365nmDUV = 248nm193 = 193nm157 = = EUV nmi-193 = 133nmAgenda Introduction to cmos vlsi Technology Physics Challenges to Continued vlsi Scaling Gate insulator Gate electrode Carrier scattering Quantum behavior of carriers in the presence of stress Non-equilibrium Boltzmann transport Tunneling Discrete positioning of dopant atoms Electrostatics Simulation Conclusion Introduction to cmos vlsi Technology Physics Challenges to Continued vlsi Scaling Gate insulator Gate electrode Carrier scattering Quantum behavior of carriers in the presence of stress Non-equilibrium Boltzmann transport Tunneling Discrete positioning of dopant atoms Electrostatics Simulation ConclusionVoltage Reduction Achieved by Reduction in tox 10A in 2004 Increase in oxusing Plasma Nitrided Oxide (PNO)Gate InsulatorDelay~Power 1/2 CV2 FcCVIdriveInversion LayerChargeQinv Dox= oxEox oxVddtoxGate Leakage Oxide Thickness (A)nMOS Gate Current (A/cm2)SiONSiO2 Supply Voltage (Vdd)1980199020001 V5 VClock Frequency (MHz) 198019902000101001,00010,000 Gate InsulatorBad NewsDielectic ConstantBreakdown Strength (MV/cm)TiO2(k=60-95) (k= )HfO2(k=21), ZrO2(k=29)Si3N4(k= ), Al2O3(k=9)Ta2O5(k=19-26), La2O3(k=27), Pr2O3(k=31)SrTiO3(k=50-200)Hi-k also degrades channel mobilityGood NewsEOT (nm) SiSC '02 HfSiON/TI HfSiON/Toshiba vlsi '03 HfSiON/Toshiba IWGI '03 SiO2trendlineSiONNovel SiON/Toshiba vlsi '04 101 HfSiO/TI SiSC '02 HfSiON/TI HfSiON/Toshiba vlsi '03 HfSiON/Toshiba IWGI '03 SiO2trendlineSiONNovel SiON/Toshiba vlsi '04 Gate LeakageWork Function (eV)

5 GateMid-GapOptimum for NMOSO ptimum for PMOSV alence BandConduction Oxide10 nmTi GateSiElectrons in SiModern CMOSV ertical Field E MV/cmStark Quantization results in E 75 meV Vt 50 mVModern CMOSV ertical Field E MV/cmStark Quantization results in E 75 meV Vt 50 mVStark EffectE7E2E1E0 2E21E11E01E31 E= E10- E0 4 4 2[001][010][100]Effect of StrainBi-axial tensile strain of GPa results in Estrain 135 meVMobility increase 80%Idriveincrease 20%Bi-axial tensile strain of GPa results in Estrain 135 meVMobility increase 80%Idriveincrease 20%E7E2E1E0 2E21E11E01E31210 meV 4 Holes in [110] Uniaxially Compressed SiSikxky| px,py>Unstrained Heavy Hole (HH)Unstrained Heavy Hole (HH)[110]kxkyStrained Heavy Hole (HHS)Strained Heavy Hole (HHS)LH,HHHHSLHS| s,px,py,pz>Mobility ImprovesMobility DegradesDiscrete Channel Dopants Introduce IOFFF luctuationsand IOFFD egradationW = 40nmECCurrent DensityOff-CurrentFilamentIDSVGSD iscreteAverageContinuumChannel DopingL = 20nm5 XDiscreteDopingDiscrete Channel DopantsMyth of the MOSFET SwitchLog IoffVGVt s In the Off StateID~ eIn the Off StateID~ e-q s kT log ID VGqkT=Cox+ CPCoxlog10e s VGSub-Threshold Slope 60 - 100 mV/decadeFor Vt= 300mV 5 - 3 decadesIon 1 mA/umIoff 10 nA/um - 1 uA/umSub-Threshold Slope 60 - 100 mV/decadeFor Vt= 300mV 5 - 3 decadesIon 1 mA/umIoff 10 nA/um - 1 uA/umElectrostaticsCritical Scaling ParametersLWtoxxjunxdepMulti-Gate FETs show promise of extending scaling for several generations beyond planar cmos toxand xdepare encountering scaling limits.

6 This results in .. Degraded sub-threshold slope Increased drain induced barrier lowering (DIBL)kTqCox+ CPCoxConclusion Scaling cmos to the End of Roadmap will require sophisticated condensed matter Physics . Gate stack: Atomic and electron orbital understanding of this complex material system Quantum behavior of carriers High perpendicular E field Stress Non-equilibrium Boltzmann transport Tunneling: Gate insulator and Drain-to-Substrate Simulation Sophisticated condensed matter Physics will also be required to invent and develop electronics beyond cmos Single Electron Transistor (SET) Carbon Nano-tube (CNT) Molecular Electronics Spintronics Quantum Computing Scaling cmos to the End of Roadmap will require sophisticated condensed matter Physics . Gate stack: Atomic and electron orbital understanding of this complex material system Quantum behavior of carriers High perpendicular E field Stress Non-equilibrium Boltzmann transport Tunneling: Gate insulator and Drain-to-Substrate Simulation Sophisticated condensed matter Physics will also be required to invent and develop electronics beyond cmos Single Electron Transistor (SET) Carbon Nano-tube (CNT) Molecular Electronics Spintronics Quantum Computing

Show more

Documents from same domain

Diversity Considerations for Graduate Admissions - APS …

Diversity Considerations for Graduate Admissions - APS …

www.aps.org

Diversity Considerations for Graduate Admissions Casey W. Miller cwmsch@rit.edu Rochester Institute of Technology ... • State of Physics ... Top African American PhDs . 2006-2010 : University of California- Berkeley . 8 :

  American, Graduate, Admission, Institute, Physics, Considerations, Diversity, Of physics, Diversity considerations for graduate admissions

The string theory landscape - APS Physics

The string theory landscape - APS Physics

www.aps.org

at high energy, in string theory the extended nature of the string softens the high energy scattering, yielding a theory with good ultraviolet behavior. 3. 2) Simple versions of the theory have naturally massless (or very light, compared to Planck scale) Yang-Mills fields. Simple

  Theory, String, String theory

Case Studies - APS Home

Case Studies - APS Home

www.aps.org

May 09, 2007 · Case studies developed by the APS Task Force on Ethics Education Edited by Heide Doss and Gabriel Popkin Illustrations and design by Nancy Bennett-Karasik **Please print this document double-sided, if possible Teacher Edition A set of ethics case studies from physics research, with an activity

  Studies, Case, Case studies

QUANTUM ENTANGLEMENT - APS Physics

QUANTUM ENTANGLEMENT - APS Physics

www.aps.org

Holt and Pipkin – Harvard -1973. The results agreed with classical physics – never published. Due to a distortion in the vacuum chamber windows? E. Fry – U. Texas – 1973. Agreed with quantum mechanics, but not statistically significant. J. Clauser – U.C. Berkeley – 1976. Gave the first convincing violation of Bell’s inequality.

  Physics, Holt

Case Studies - APS Home

Case Studies - APS Home

www.aps.org

May 09, 2007 · Note: The ethics case studies were prepared by a special APS Task Force on Ethics Education to promote discussion of these issues. Some of the studies were also contributed by the general population. They are based on the views of the task force members, and should not be considered to be the views of APS as a whole.

  Studies, Case, Some, Case studies

Related documents

Lecture 1: Circuits & Layout - cmosvlsi.com

Lecture 1: Circuits & Layout - cmosvlsi.com

www.cmosvlsi.com

CMOS VLSI Design Lecture 1: Circuits & Layout David Harris Harvey Mudd College Spring 2004. 1: Circuits & Layout CMOS VLSI Design Slide 2 Outline qA Brief History qCMOS Gate Design ... Circuits & Layout CMOS VLSI Design Slide 45 Gate Layout qLayout can be very time consuming – Design gates to fit together nicely

  Lecture, Circuit, Layout, Cmos, Vlsi, Lecture 1, Cmos vlsi, Circuits amp layout, Cmosvlsi

Fundamentals of CMOS VLSI 10EC56 - Weebly

Fundamentals of CMOS VLSI 10EC56 - Weebly

vmracetechnology.weebly.com

Fundamentals of CMOS VLSI 10EC56 CITSTUDENTS.IN Page- 4 3 UNIT 3: CMOS LOGIC STRUCTURES 67-78 CMOS Complementary Logic, 67 Bi CMOS Logic 67-68 Pseudo-nMOS Logic 69-70 Dynam icCMOS Log 71 CMOS D omin Log icC asca de V l tge Sw h g (CVSL).

  Fundamentals, Cmos, Vlsi, Fundamentals of cmos vlsi 10ec56, 10ec56

Lecture 9: Circuit Families - cmosvlsi.com

Lecture 9: Circuit Families - cmosvlsi.com

www.cmosvlsi.com

CMOS VLSI Design Lecture 9: Circuit Families David Harris Harvey Mudd College Spring 2004. 9: Circuit Families CMOS VLSI Design Slide 2 Outline qPseudo-nMOS Logic qDynamic Logic ... Circuit Families CMOS VLSI Design Slide 25 Leakage qDynamic node floats high during evaluation – Transistors are leaky (I

  Lecture, Circuit, Cmos, Families, Lecture 9, Vlsi, Cmos vlsi, Cmosvlsi, Circuit families

Analog CMOS/VLSI Design - USF

Analog CMOS/VLSI Design - USF

ugs.usf.edu

USF: Analog CMOS VLSI Design. Spring 2014 1 Catalog Description: Design of analog circuits for CMOS/VLSI design. Op-amps, comparators, D to A and A to D converters. Switched capacitor filters.

  Design, Analog, Cmos, Vlsi, Analog cmos vlsi design, Cmos vlsi

Iddq Testing for CMOS VLSI - cs.colostate.edu

Iddq Testing for CMOS VLSI - cs.colostate.edu

www.cs.colostate.edu

Iddq Testing for CMOS VLSI Rochit Rajsuman, SENIOR MEMBER, IEEE It is little more than 15-years since the idea of Iddq testing was first proposed. Many semiconductor companies now consider Iddq

  Testing, Cmos, Vlsi, Cmos vlsi, Iddq testing, Iddq

Lecture 14: Wires - User page server for CoE

Lecture 14: Wires - User page server for CoE

user.engineering.uiowa.edu

14: Wires CMOS VLSI Design 4th Ed. 22 Crosstalk Delay Assume layers above and below on average are quiet – Second terminal of capacitor can be ignored – Model as C gnd = C top + C bot Effective C adj depends on behavior of neighbors

  Wire, Cmos, Vlsi, Wires cmos vlsi

CMOS Transistor Theory - pages.hmc.edu

CMOS Transistor Theory - pages.hmc.edu

pages.hmc.edu

3: CMOS Transistor Theory 3CMOS VLSI DesignCMOS VLSI Design 4th Ed. Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current

  Theory, Transistor, Cmos, Vlsi, Cmos transistor theory

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

ece.tamu.edu

Agenda • MOS Fabrication Sequence • CMOS Design Rules • Layout Techniques • Layout Examples 3

  Design, Analog, Circuit, Cmos, Vlsi, Ecen474 704, Ecen474, Vlsi circuit design

CMOS VLSI Design - Harvey Mudd College

CMOS VLSI Design - Harvey Mudd College

pages.hmc.edu

Fourth Edition Neil H. E. Weste Macquarie University and The University of Adelaide David Money Harris Harvey Mudd College CMOS VLSI Design A Circuits and Systems Perspective

  Design, Cmos, Vlsi, Cmos vlsi design

CMOS VLSI Design Techniques - University of Southern ...

CMOS VLSI Design Techniques - University of Southern ...

www-classes.usc.edu

designs&that&are&highly&optimized&but&are&too&late&for&products&that&have&planned& timing.&&& Thefinalchallengeisonethatkeeps theauthorinterestedinteachingwhatappears&

  Design, Technique, Cmos, Vlsi, Cmos vlsi design techniques

Related search queries

Lecture 1: Circuits & Layout, Cmosvlsi, CMOS VLSI, Fundamentals of CMOS VLSI 10EC56, CMOS, Lecture 9: Circuit Families, Analog CMOS/VLSI Design, Analog CMOS VLSI Design, CMOS/VLSI, Iddq testing, 14: Wires, 14: Wires CMOS VLSI, CMOS Transistor Theory, VLSI, ECEN474/704: (Analog) VLSI Circuit Design, CMOS VLSI Design, CMOS VLSI Design Techniques