PI7C9X2G404SL - Diodes Incorporated

1 Document Number DS40068 Rev 2-2 PI7C9X2G404SL PCI EXPRESS GEN 2 PACKET SWITCH 4-Port, 4-Lane, SlimPacket Packet Switch DATASHEET REVISION 2- 2 September 2017 1545 Barber Lane Milpitas, CA 95035 Telephone: 408-232-9100 FAX: 408-434-1040 Internet: i o de om PI7C9X2G404SL Page 2 of 90 September 2017 Document Number DS40068 R ev 2-2 w ww .d iodes .com D i odes Incor por ated PI7C9X2G404SL IM PORT A NT NOT IC E D IO D ES IN CO R PORA T ED MA K ES N O WA RRA N TY OF A NY KIND, EX PR ES S OR IMPL IED, W IT H R EGA R DS TO TH IS DO CU MEN T, IN CL UD ING, B U T N OT L IMIT ED TO, TH E IMPL IED WA R RA NT IES O F MERC HA NTA B IL ITY A ND F ITN ESS F OR A PA RTICULA R PURPOSE ( A ND THEIR EQUIV A LENTS UNDER THE LA WS OF A NY JURISDICT ION).

2 Diodes Incorporated and its subsidiaries reserve the right to make modif ications, enhancements, improvements, corrections or other changes w ithout f urther notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume all risks of such use and w ill agree to hold Diodes Incorporated and all the companies w hose products are represented on Diodes Incorporated w ebsite, harmless against all damages.

3 Diodes Incorporated does not w arrant or accept any liability w hatsoever in respect of any products purchased through unauthorized sales channel. Should Customers purchase or use Diodes Incorporated products f or any unintended or unauthorized application, Customers shall indemn if y and hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of , directly or indirectly, any claim of personal injury or death associated w ith such unintended or unauthorized application. Products described herein may be covered by one or more United States, international or f oreign patents pending. Product names and markings noted herein may also be covered by one or more United States, international or f oreign trademarks.

4 This document is w ritten in English but may be translated into multiple languages f or ref erence. Only the English version of this document is the f inal and determinative f ormat released by Diodes Incorporated . LIFE SUPPORT Diodes Incorporated products are specif ically not authorized f or use as critical components in lif e support devices or systems w ithout the express w ritten approval of the Chief Executive Of f icer of Diodes Incorporated . As used herein: A. Lif e support devices or systems are devices or systems w hich: 1. are intended to implant into the body, or 2. support or sustain lif e and w hose failure to perf orm w hen properly used in accordance w ith instructions f or use provided in the labeling can be reasonably expected to result in signif icant injury to the user.

5 B. A critical component is any component in a lif e support device or system w hose f ailure to perf orm can be reasonably expected to cause the f ailure of the lif e support device or to af f ect its saf ety or ef f ectiveness. Customers represent that they have all necessary expertise in the safety and regulatory ramif ications of their lif e support devices or systems, and acknow ledge and agree that they are solely responsible f or all legal, regulatory and saf ety-related requirements concerning their products and any use of Diodes Incorporated products in such saf ety-critic al, lif e support devices or systems, notw ithstanding any devices- or sys tems-related inf ormation or support that may be provided by Diodes Incorporated .

6 Further, Customers must f ully indemnif y Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such saf ety-critical, lif e support devices or systems. Copyright 2016, Diodes Incorporated www. d i o de s . c o m PI7C9X2G404SL Page 3 of 90 September 2017 Document Number DS40068 R ev 2-2 w ww .d iodes .com D i odes Incor por ated PI7C9X2G404SL REVISION HISTORY Date Revision Number Description 06/09/10 Preliminary Dat asheet 10/19/10 Added Section 6 EEPROM Interface And Sy stem M anagement Bus Added Section 7 Regist er Descrip t ion 07/12/11 Added Industrial Temp erature Sup p ort (Section 1 Features, Section Absolute M aximum Ratings, Section 13 Ordering Information) 11/23/11 Up dat ed Sect ion 1 Feat ures (int egrat ed reference clock) Up dated Section PCI Exp ress Interface Signals (Added REFCLKI_P, REFCLKI_N, REFCLKO_P[3:0], REFCLKO_N[3.)]

7 0], and IREF) 06/27/12 Up dat ed Sect ion Port Configuration Signals (RXP OLINV_DIS) Up dat ed Sect ion M iscellaneous Signals (TEST4 and TEST5) 07/25/12 Up dat ed Sect ion 1 Feat ures (OBFF and LTR sup p ort) Up dated Section 3 Pin Descrip tion (RXP OLINV_DIS, P RSNT[3:1] , TEST4, T EST5, and CVDDR) Up dat ed Sect ion 6 EEPROM Int erface And Sy st em M anagement Bus Up dat ed Sect ion 7 Regist er Descrip t ion 01/02/13 Up dated Section 3 Pin Descrip tion (PWR_SAV, TCK, and TRST_L) Added Section AC Swit ching Charact erist ics of Clock Buffer Up dat ed T able 8-1 Clock Requirement Up dated Table Power Pins Up dated Table Pin List of 129-Pin LQFP 07/15/14 Up dated Section 1 (512-by t e maximum p ay load siz e sup p ort, No-blocking cap abilit y ) Up dat ed Sect ion Port Configuration Signals Up dat ed Sect ion Miscellaneous Signals Up dated Section Phy sical Lay er Circuit Up dated Section Drive De-Emp hasis Up dated Section Device Cap abilities Regist er (M ax_Pay load_Size Sup p orted)

8 Up dated Section 13 Ordering Information Up dat ed T able 11-2 DC Elect rical Charact erist ics 10/22/14 Up dated Section 13 Ordering Information 11/17/14 Up dated Section Transp arent M ode Configuration Registers Up dated Section 8 Clock Scheme 07/16/15 Up dat ed Section PCI Exp ress Interface Signals Up dat ed Sect ion Port Configuration Signals Up dat ed Sect ion Phy sical Lay er Circuit Up dated Section EEPROM Interface Up dat ed Section Transp arent M ode Configuration Registers Up dat ed Section 8 Clock Scheme Up dat ed T able 9-1 Instruction Register Codes Up dated T able 9-2 JTAG Device ID Register Up dat ed T able 9-3 JTAG Boundary Scan Register Definition Up dat ed T able 11-2 DC Elect rical Charact erist ics 09/07/15 Up dat ed T able 11-1 Absolute M aximum Ratings 12/23/15 Up dat ed Section 3 PIN Descrip tion Up dat ed T able 11-1 Absolute M aximum Ratings Up dat ed T able 11-2 DC Elect rical Charact erist ics 03/04/16 Added Sect ion 11 Power Sequence Up dated Section Pin List Of 128-Pin LQFP 05/12/17 Up dat ed Sect ion Absolute Maximum Rat in gs Added Section Op erating Ambient Temp erature Up dat ed Sect ion Op erating Ambient Temp erature Added Section Power Consump tion 08/29/17 2-2 Up dat ed Sect ion 1 Feat ures Up dated Section Port Configuration Signals Up dated Section Phy sical Lay er Circuit Updated Section M ap p ing EEPROM Contents to Configuration Registers Up dated Section Transp arent M ode Configuration Registers Up dated Section Absolute M aximum

9 Ratings Up dat ed T able 12-2 DC Elect rical Charact erist ics PI7C9X2G404SL Page 4 of 90 September 2017 Document Number DS40068 R ev 2-2 w ww .d iodes .com D i odes Incor por ated PI7C9X2G404SL Added Section Op erating Ambient Temp erature Added Section Power Consump tion Revision numbering sy stem changed to whole number PI7C9X2G404SL Page 5 of 90 September 2017 Document Number DS40068 R ev 2-2 w ww .d iodes .com D i odes Incor por ated PI7C9X2G404SL TABLE OF CONTENTS 1 FE A T U R ES .. 10 2 GEN ERAL DES CRIPTION .. 11 3 PIN DES CRIPTION .. 13 PCI EX P R ES S INTERFACE SI GNA LS .. 13 PO RT CO NF I GU RA TI ON SI GNA LS .. 14 MISCELLANEOUS S I GNA 14 JTA G BOUNDARY S CA N S I GNA LS .. 15 POW ER PI NS .. 16 4 PIN AS S IGN MEN TS .. 17 PIN LIST OF 1 28-P IN LQF P.

10 17 5 FUNCTIONAL DES CRIPTION .. 18 PH YS ICA L LA YE R CIRCUIT .. 18 RECEIVER DE TECTION .. 18 RECEIVER SIGNA L DETEC TION .. 18 RECEIVER EQUA LIZATION .. 19 TRANSMITTER S WING .. 19 DRIV E AMP LITUDE AN D DE-EMP HASIS SETTINGS .. 19 DRIV E AMP 20 DRIV E DE-EMP HASIS .. 21 TRANSMIT TER E LECTR ICAL IDLE LA TENCY .. 21 DA TA LI N K LA YE R (DLL) .. 21 TRANSACTION LA YE R RECEIVE BLOCK (T LP DECAPSULATION) .. 22 ROUT IN G .. 22 TC/ VC MAPPING .. 22 QUEUE .. 22 PH .. 23 PD .. 23 NPHD .. 23 CPLH .. 23 CPLD .. 23 TRANSACTION ORDERING .. 23 PO RT ARBITRATION .. 24 VC A R BIT RA TI O N .. 24 F LOW CONTROL .. 24 TRANSATION LA YE R TRANSMIT BLOCK (T LP ENCAPSULATION) .. 25 6 EEPROM INTERFACE AND S YS TEM MANAGEMENT 26 EEPROM I NT ERFA C E.