第三章 Pipelined MIPS CPU 規劃設計 - ntnu.edu.tw

1 Pipelined MIPS CPU .. MIPS MIPS CPU. R-Type . 3-1 3-2 . 21 4 25 . 3-1 . Encoding Encoding Inst. Type Mnemonic 31 26 25 21 20 16 15 11 10 6 5 0. LW 100011 sssss Ttttt iiiii iiiii iiiiii M. SW 101011 sssss ttttt iiiii iiiii iiiiii M. ADD 000000 sssss ttttt ddddd 00000 100000 R. ADDU 000000 sssss ttttt ddddd 00000 100001 R. SUB 000000 sssss ttttt ddddd 00000 100010 R. SUBU 000000 sssss ttttt ddddd 00000 100011 R. AND 000000 sssss ttttt ddddd 00000 100100 R. OR 000000 sssss ttttt ddddd 00000 100101 R. XOR 000000 sssss ttttt ddddd 00000 100110 R. NOR 000000 sssss ttttt ddddd 00000 100111 R. SLL 000000 sssss ttttt ddddd hhhhh 000000 R. SRL 000000 ----- ttttt ddddd hhhhh 000010 R. SRA 000000 ----- ttttt ddddd hhhhh 000011 R. ADDI 001000 sssss ttttt iiiii iiiii iiiiii I. ADDIU 001001 sssss ttttt iiiii iiiii iiiiii I. ANDI 001100 sssss ttttt iiiii iiiii iiiiii I. ORI 001101 sssss ttttt iiiii iiiii iiiiii I. XORI 001110 sssss ttttt iiiii iiiii iiiiii I.

2 BEQ 000100 sssss ttttt iiiii iiiii iiiiii B. BNE 000101 sssss ttttt iiiii iiiii iiiiii B. J 000010 iiiii iiiii iiiii iiiii iiiiii J. 010001 sssss ttttt ddddd 00000 000001 R. 010001 sssss ttttt ddddd 00000 000010 R. 010001 sssss ttttt ddddd 00000 000011 R. 010001 sssss ttttt ddddd 00000 000100 R. 16. 3-2 . NO. Mnemonic OP Code Syntax Operation 1 LW 100011 lw $t, offset($s) $t=MEM[$s+offset]. 2 SW 101011 sw $t, offset($s) MEM[$s+offset] =$t 3 ADD 000000 add $d, $s, $t $d =$s + $t 4 ADDU 000000 addu $d, $s, $t $d =$s + $t 5 SUB 000000 sub $d, $s, $t $d =$s - $t 6 SUBU 000000 subu $d, $s, $t $d =$s - $t 7 AND 000000 and $d, $s, $t $d =$s & $t 8 OR 000000 or $d, $s, $t $d =$s | $t 9 XOR 000000 xor $d, $s, $t $d =$s ^ $t 10 NOR 000000 nor $d, $s, $t $d = ~($s | $t). 11 SLL 000000 sll $d, $t, shamt $d =$s << shamt 12 SRL 000000 srl $d, $t, shamt $d =$s >> shamt 13 SRA 000000 sra $d, $t, shamt $d =$s >> shamt 14 ADDI 001000 addi $t, $s, immed $t =$s + immed 15 ADDIU 001001 addiu $t, $s, immed $t =$s + immed 16 ANDI 001100 andi $t, $s, immed $t =$s & immed 17 ORI 001101 ori $t, $s, immed $t =$s | immed 18 XORI 01110 xori $t, $s, immed $t =$s ^ immed 19 BEQ 000100 beq $s, $t, offset if $s==$t advance_pc 20 BNE 000101 bne $s, $t, offset if $s!

3 =$t advance_pc 21 J 000010 j Target pc=pc&(000000| target). 22 010001 $d, $s, $t $d =$s + $t 23 010001 $d, $s, $t $d =$s - $t 24 010001 $d, $s, $t $d =$s $t 25 010001 $d, $s, $t $d =$s $t 17. IF Stage . Instruction Fetch IF IF . 3-1 Pipelined MIPS CPU IF . b r a n c h C tl jm p A d d r mux b r a n c h A d d r jm p C tl ID _ P C 4. R E G. 4. S ta ll S ta ll P C _ I n s tr u c tio n ID _ IR. R E G M em o r y R E G. F lu s h F lu s h 3-1 IF Stage . 1 PC_REG IM. Instruction Memory . 2 Stall Flush . PC .. IF Stage Cycle PC . Beq Bne Jmp . PC PC+4 Beq Bne Jmp . PC . Instruction PC PC . Memory .. Instruction Memory 256 32 Bits . Block RAM Block RAM Xilinx ISE Core Generator . [9] . 18. ID Stage . Instruction Decode ID ID . 3-2 Pipelined MIPS CPU ID. Block . STALL. STALL. Hazard detection Unit 0 EX _ctl Control jm pAddress jm pAddr PC+4. BranchAddr beq/bne BranchC tl Shift left 2. EX _IR. R EG. Instr[25-21] EX _. Read1 Data1.

4 Instr[31-0]. D ata1. Instrt[20-16]. Read2 R EG. REG ISTER. Equal Bank EX _. W addr Data2 D ata2. W addr R EG. exe_dout W data W data mem_dout RegW rite wb_dout EX _. R egW rite Sign R EG. SignE xtend Instr [20-16] EX _. RT. EXE_RD Forw arding R EG. M EM _R D. Unit W B_RD. EX _. Instr [15-11] RD. R EG. EX _. Instr [25-20]. RS. R EG. 3-2 ID Stage . 19. Control Unit Decode .. Register Bank 32 GPR 32-bits . 3-3 Register Bank . 32 .. Data1 Data2 MIPS CPU ALU . RegDout I/O . MIPS CPU Register Bank 5 32 Decoder . RegWrite Waddr 32 . [23] . Register Bank Read2. Read1. Reset RESET Register(0). clk CLOCK M. DO0.. WEN U Data1. Wdata DI. X. Register(1). DO1. to ALU. Register(2) M.. U Data2.. DEC_OUT0 X. DEC_OUT1.. RegWrite DEC_IN5x32. Waddr Decoder M.. Register(31) U RegDout to I/O. DEC_OUT31 DO31 X. RegSel 3-3 Register Bank . Sign Extend 0~15bits 32bits EXE. Stage Immediate Branch Address . Jmp Address Jamp . Shift Left 2 Branch.

5 Equal Branch . 20. Forward Unit EXE MEM . WB forwarding ID .. Hazard Detection Unit Load-use Data Hazard .. EXE Stage . Instruction Execute EXE EXE Stage .. EXE Stage 3-4 Block . E X .F lu s h 0 M E M _. E X _ C tl C T L. F P .g o F P .g o F P .d a ta 1 F P .d o u t dout F P .d a ta 2 F P .u n d FP_. F P .o v addr F P _ U N IT out F P .f u n c F P .d o n e done M E M _. E X _ In s tr IR. A L U S rc R E G. E X _ D a ta 1. Mux W B _D out M E M _D out M E M _. ALU. E X _ D a ta 2 A L U. Mux R e s u lt Mux R E G. A L U O p E X _ S ig n A L U. M E M _ R e g W r ite C tl F o rw a rd in g M E M _. W B _ R e g W rite U n it D a ta 2. R E G. MEM_RD. WB_RD. EX_RS. 0. E X _R T M E M _. M ux EX _R D R D. 1 R E G. R egD st 3-4 EXE Stage . 21. ALU MIPS CPU . ALU . ALU . 3-5 Barrel Shifter . Mano[20] . Shift Left Shift Right .. Barrel Shifter . 3-6 SHIFT_FUNC 3-3 . ALU. A LU _C TR L. R S_IN. A DD. R T_IN. SU B. A ND Z ero ZER O _FLA G.

6 D etect M. OR U A LU _OU T. X. XO R O verflow O VF _FLA G. D etect NO R. A LU _C TR L B arrel SH A M T. Shifter A C om pare A>B LA RG E _FLA G. A<B EQ U AL _FL AG. B U nit A=B SM A LL_FL AG. 3-5 ALU . Barrel Shifter SHIFT_FUNC[0] EN SHIFT_FUNC. SHIFT_FUNC[1] Shift SHIFT_TIMES Right SHIFT_DIN Logical ENShift 0. Left 1 SHIFT_DOUT. Logical 2. ENShift Right Arithmetic 3-6 Barrel Shifter . 22. 3-3 SHIFT_FUNC[1:0] Encoding Encoding SHIFT_. Function Shift Mode FUNC[1:0]. SHIFT_OUT[31:0] =. SRL Shift Right Logical 00. SHIFT_IN srl (SHIFT_TIMES). SHIFT_OUT[31:0] =. SLL Shift Left Logical 01. SHIFT_IN sll (SHIFT_TIMES). SHIFT_OUT[31:0] =. SRA Shift Right Arithmetic 10 11. SHIFT_IN sra (SHIFT_TIMES). ALU CTL ALU ALU . R-Type I-Type ALU . R-Type Function Code OP Code ALU . ALU ALU ALU_OP. ALU_FUNC 3-4 3-5 ALU 3-4. 3-5 ALU . [23] . 3-4 ALU_OP Encoding Encoding ALU_OP[3:0]. Mnemonic or Function R-TYPE 0010. ADDI 0011. ADDIU 0100.

7 I-TYPE ANDI 0101. ORI 0110. XORI 0111. B-TYPE 0001. Program Counter ADD 0000. Program Counter SUB 0001. 23. 3-5 ALU_FUNC[5:0] Encoding Encoding ALU_FUNC[5:0]. Mnemonic ADD ADDI ADDIU 100000. ADDU 100001. SUB 100010. SUBU 100011. AND ANDI 100100. OR ORI 100101. XOR XORI 100110. NOR 100111. - SLL 000000. SRL 000010. SRA 000011. Forward Unit MEM WB . forwarding EXE ALU .. Floating Unit . MEM Stage . Data Memory MEM MEM Stage Data Memory DM 3-7 DM . 256 32 Bits Block RAM Block RAM Xilinx ISE Core Generator Mem Write DM . 24. M EM _C TL. W B _C TL. M E M _ I n s tr W B _ IR R E G. M e m W r ite M E M _ A L U R e s u lt R ead W B _ R e a d D a ta A ddr D a ta REG. DATA M EM ORY. M E M _ D a ta 2. W r ite d a ta W B _ A L U R e s u lt REG. M EM _R D W B _R D R E G. 3-7 MEM Stage . WB Stage . Write Back WB WB Stage . Register Bank 3-8 MemtoReg . Data Memory ALU . WB_RegWrite WB_RD ID Stage Register Bank . W B _ R e g W rite M e m to R e g W B _ R e a d D a ta 1.

8 Mux W B _ A L U R e s u lt 0. W B _ R D. 3-8 WB Stage . 25. Control Unit . CU ID Stage . ID/EXE 3-9 . 3-9 Control Unit . 1 ALUOp ALU . 2 ALUSrc ALU Register Bank . 3 RegDst Rt Rd . 4 LW MemtoReg . 5 R-type Lw I-type RegWrite . 6 Sw MemWrite . 7 Beq Branch . 8 Bne nBranch . 9 Jmp . 10 F_GO . Flush 1 . Stall 1 ALUOp ALUSrc RegDst MemtoReg RegWrite . MemWrite Stall nop .. 26. Pipelined Control . Hazard CPU . Structural Hazard . Harvard Architecture .. IF Stage MEM Stage . Structural Hazard . ID Stage WB Stage Register Bank .. Structural Hazard . Structural Hazard . Clock Clock . Register Bank Register Bank . Structural Hazard 3-10 . C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C13 C14 C15 C16. I1 IF ID EXE MEM WB. I2 IF ID EXE1 EXE2 EXE3 EXE4 EXE5 EXE6 EXE7 EXE8 WB. (Floating Ins.). I3 IF ID EXE MEM WB. I4 IF ID EXE MEM WB. I5 IF ID EXE MEM WB. I6 IF ID EXE MEM WB. I7 IF ID EXE MEM WB. I8 IF ID EXE MEM Bubble WB. I9 IF ID EXE Bubble MEM WB.

9 I10 IF ID Bubble EXE MEM WB. I11 IF Bubble ID EXE MEM WB. F_WB. 3-10 . 27. I1~I11 I2 8 . Clock Register Bank . MEM. Stage Register Bank Clock . EXE Stage F_done assert .. Clock . Clock I8 Clock I9 I10 I11 Clock . Data Hazard . 3-11 . Case1: I2 EXE I1 EXE . Case2: I3 EXE I1 EXE . MEM Data Memory . Case3: I1 Load I2 EXE I1 . MEM Data Memory . Case4: I2 Branch ID I1 EXE.. Case5: I3 Branch ID I1 EXE.. 28. 3-11 Data Hazard . Data Hazard Case1 Case2 Case4 Case5. Data Hazard Forwarding Unit 3-12 . ID EXE MEM WB. MEM_. CTL. clk reset MemtoReg Read1 Data1 EX_. Mux Data1. REG. Read2 MEM_ WB MemtoReg ALU Addr _CTL. Equal Result REGISTERS REG. Read EX_ 1. Data Data2 Data2. Mux Waddr 0. REG. Mux DATA WB_. Wdata MEMORY Read 1. 1. ALUOp Data 4 REG. EX_ 0. ALU. Mux Sign Ctl REG. Write MEM_. data Data2 WB_. REG ALU 2. Result EX_ REG. RT. 0. REG. Forwarding M. u MEM_ 1 5. RD. Unit x REG. 1 WB_. EX_ RD. RD REG. REG. Forwarding Unit EX_.

10 RS. REG. 3-12 Forwarding . 29. Case 3 Data Hazard Load-use Data Hazard . Forwarding Hazard Detection Unit . Hazard Detection Unit ID . Load 3-13 . Load-use Data Hazard I2 ID C3 Hazard Detection Unit I1 Load I2 . I1 . Hazard Detection Unit Flush 1 I2 . Interlock Clock C4 I2 . I2 EXE C5 . I1 Data Memory I2 Forwarding Unit . C1 C2 C3 C4 C5 C6. I1 MEM. IF ID EXE WB. Load Ins. Hazard I2 IF ID Bubble Bubble Bubble Interlock ID EXE MEM WB. I3 IF ID EXE MEM WB. Interlock Inst. Reg I1 I2 I3 . 3-13 Load-use Data Hazard . 30. Control Hazard . Branch .. Stall . Branch ID . Data Hazard 3-14 I1~I5 . 5 I4 I3 Data Dependence I2 I2 Load . I4 ID C5 .. IF PC C6 IF. ID EXE . Flush . C1 C2 C3 C4 C5 C6 C7 C8 C9 C10. I1 IF ID EXE MEM WB. I2 IF ID EXE MEM WB. IF ID EXE MEM WB. I3. Taken I4 IF ID Bubble Bubble Bubble Branch/Jmp Ins. I5 IF Flush Bubble Bubble Bubble New Branch Target Ins. PC IF ID EXE MEM WB. PC Value X X+4 X+8 X+12 X+16 X'.