PPA Printer Controller ASIC Development - hpl.hp.com

1 Article 4 June 1997 Hewlett-Packard Journal 1 PPA Printer Controller ASICD evelopmentAs the first Printing Performance Architecture Printer , the HPDeskJet 820C needed a completely new digital Controller ASIC design. The chip s architecture was optimized for the specificrequirements of PPA. Concurrent Development of hardware andfirmware through the use of hardware emulators and attention toregulatory issues during the design helped the product meet all ofits requirements on John L. McWilliams, Leann M. macmillan , Bimal Pathak, and Harlan A. TalleyThe Printing Performance Architecture (PPA) used in the HP DeskJet 820C Printer is a significant step forward from anyprevious HP inkjet Printer product in providing the consumer with a high-performance product at an excellent price PPA redistributes the printing tasks between the host and the Printer , a complete redesign of the digital controllerASIC in the Printer was required.

2 This redesign effort took into account the overall product constraints of cost and time tomarket as well as all applicable government regulations. The result is a highly integrated ASIC that implements all digitalfunctions performed by the HP DeskJet 820C on a single chip. This high level of integration significantly decreased the costof the electronics in the HP DeskJet 820C compared to the previous-generation product while maintaining the Printer sperformance. This article describes the system considerations, engineering decision trade-offs, and developmentmethodologies that played a role in the Development of the digital Controller ASIC for the HP DeskJet design of the Controller ASIC had to be done under numerous constraints. As in any consumer-oriented product, theforemost consideration during design was the final cost to the buyer.

3 The Performance Printer Architecture, as described inArticle 1, was developed to reduce the total cost of the Printer . PPA allows several optimizations in the digital today s competitive environment, time to market is nearly as critical a constraint as cost. Meeting the time-to-marketconstraint required concurrent Development of hardware and firmware and a bug-free ASIC at netlist release. These needswere addressed by using hardware emulators during Development . Finally, the Printer had to meet or exceed all governmentregulations including those pertaining to EMI and ESD. Taking these needs into account during the ASIC design helped theproduct pass all requirements on ArchitectureRegardless of their specific type, all printers require several pieces of digital hardware.

4 These pieces include amicroprocessor to control the Printer , RAM for data, ROM for firmware, and custom digital logic for Printer -specificfunctions. By optimizing each of these pieces, significant cost savings were realized in the digital significantly reduces the cost of the Printer by optimally partitioning the printing tasks between the software runningon the host and the hardware and firmware running in the Printer . The partitioning is done without sacrificing the Printer sperformance. All tasks that can be done on the host computer without severely affecting application performance are donein the driver. Tasks with real-time constraints are performed by the hardware and firmware in the Printer . Because the hostperforms the majority of the data manipulation, data that is sent to the Printer is in a format that is very close to the finalform used to fire the printheads.

5 Because of this, the digital architecture was designed with a guiding principle of theprocessor does not touch the data. Once this principle was adopted, the ASIC team was able to make several importantdesign , a relatively low-power processor is all that is needed, since the processor does not manipulate the data. Aftersurveying the available microprocessors, the 16-MHz version of the Motorola 68EC000 was chosen as the best fit. Second,since the number of tasks the firmware performs is limited, the code size can be kept small enough that a ROM with allfirmware can be integrated on the ASIC, eliminating the need for an external flash memory or ROM. Third, all datamanipulations need to be done in hardware, which limits those manipulations to being relatively simple.

6 Finally, the memoryrequirements are limited a 1M-bit DRAM is sufficient for the data needs. The DRAM holds all firmware variables and stacksas well as all printing data. Even with the DRAM doing double duty, the memory bandwidth requirements of the architectureare fairly low, and the product is able to use a low-cost, 1M-bit, nibble-wide block diagram of the HP DeskJet 820C s digital architecture is shown in Fig. 1. The digital electronics consists of threemain components: the digital ASIC, a 1M-bit DRAM, and an optional external flash memory or ROM. The digital ASIC consists of a 68EC000 microprocessor, a 64K-byte ROM, a 55,000-gate standard cell block, and a 1K-byte SRAM used as aArticle 4 June 1997 Hewlett-Packard Journal 2data cache.

7 In addition to the external memory components, the digital ASIC is connected to the I/O connector (IEEE 1284),the Printer motor ASIC, the printhead ASIC, and an optical encoder which provides carriage position PathCarriage Position LogicMotor ControlController ASIC68EC000 Micro-processorInternalROMSRAMS tandardCellFig. 1. HP DeskJet 820C Controller ASIC block majority of the standard cell area is devoted to the data path, which is the path the data follows as it moves from theI/O connector, through the DRAM and SRAM, and up to the pen ASIC. The remaining logic is used for interfacing to themicroprocessor, for controlling motors, and for keeping track of the current carriage position. All memories, includingregisters in the standard cell block, are memory mapped into the 68EC000 s standard address or ROMThe ASIC is designed to be able to read code for the processor from one of three sources: a flash memory device, an externalmask-programmable ROM (MROM), or the internal ROM.

8 The reason for the three separate sources is to better meettime-to-market constraints. At the beginning of the manufacturing ramp, code was stored in flash memory. That way, finalfirmware did not need to be released until just before the start of the ramp. As soon as the firmware was stable, it wasreleased to both the MROM vendor and the digital ASIC vendor for programming into the internal ROM. However, MROM lead times are much shorter than general-purpose ASIC lead times, so MROM parts were available much sooner than ASIC swith properly programmed internal ROMs. Consequently, printers were built with MROMs for a period of time until ASIC swith final firmware were available (MROMs are about half the cost of flash parts).Motor ControlThe HP DeskJet 820C has three motors: a dc motor for moving the carriage across the paper, a stepper motor for picking andadvancing the paper, and a second stepper motor for controlling the pen service station.

9 The stepper motors are controlledin an open-loop process by the firmware. The firmware controls a stepper motor move by writing appropriate phase andpulse width data to registers in the ASIC. Hardware then generates the appropriate signals for the motors. The phase andpulse width data determines the direction and speed of the carriage motor is controlled by a firmware-based control loop that monitors the carriage position and adjusts the motorcontrol signals appropriately. The carriage position is determined through the use of an optical encoder. The optical encoderconsists of a light emitter-detector pair with a plastic encoder strip between them. As the carriage moves across the paper,Article 4 June 1997 Hewlett-Packard Journal 3the light emitter-detector pair senses that it is moving along the plastic strip, and sends some signals to the ASIC.

10 Thehardware in the ASIC takes this information and uses it to keep track of the current carriage position. Using the carriageposition, the firmware tracks the carriage s speed and acceleration and adjusts the motor energy I/O Packet FormatThe data from the host comes to the Printer in a simple packetized format. As shown in Fig. 2, the packets are made up oftwo pieces: header information and data. The header information consists of a start-of-packet (SOP) byte, a channel byte,and a two-byte data-size field that reflects the number of bytes in the data field (0 to 65K). Start ofPacketChannelSizeDataLast ByteFirst ByteHeaderDataFig. 2. PPA data packet the HP DeskJet 820C, packets from the host may contain one of two types of information: command data or image channel byte determines which type of data is contained in the packet (hence, in the HP DeskJet 820C, the channel bytewill be one of only two distinct values).