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PSpice Reference Guide - University of Pennsylvania

PSpiceHow to Use This Online ManualHow to print this online manualWelcomeOverviewCommandsAnalog devicesDigital devicesCustomizing device equationsGlossaryIndexReference GuideCopyright 1985-2000 Cadence Design Systems, Inc. All rights ad e ma r ksAllegro, Ambit, BuildGates, Cadence, Cadence logo, Concept, Diva, Dracula, Gate Ensemble, NC Verilog, OpenBook online documentation library, Orcad, Orcad Capture, PSpice , SourceLink online customer support, SPECCTRA, Spectre, Vampire, Verifault-XL, Verilog, Verilog-XL, and Virtuoso are registered trademarks of Cadence Design Systems, , Assura, Cierto, Envisia, Mercury Plus, Quickturn, Radium, Silicon Ensemble, and SPECCTRAQ uest are trademarks of Cadence Design Systems, is a service mark of Cadence Design Systems, other brand and product names mentioned herein are used for identification purposes only and are registered trademarks, trademarks.

Basic SPICE polynomial expressions (POLY) 136 Basic controlled source properties 136 Implementation examples 137 Current-controlled current source 139 Current-controlled voltage source 139 Basic SPICE polynomial expressions (POLY) 139 Independent current source & stimulus 140 Independent voltage source & stimulus 140

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Transcription of PSpice Reference Guide - University of Pennsylvania

1 PSpiceHow to Use This Online ManualHow to print this online manualWelcomeOverviewCommandsAnalog devicesDigital devicesCustomizing device equationsGlossaryIndexReference GuideCopyright 1985-2000 Cadence Design Systems, Inc. All rights ad e ma r ksAllegro, Ambit, BuildGates, Cadence, Cadence logo, Concept, Diva, Dracula, Gate Ensemble, NC Verilog, OpenBook online documentation library, Orcad, Orcad Capture, PSpice , SourceLink online customer support, SPECCTRA, Spectre, Vampire, Verifault-XL, Verilog, Verilog-XL, and Virtuoso are registered trademarks of Cadence Design Systems, , Assura, Cierto, Envisia, Mercury Plus, Quickturn, Radium, Silicon Ensemble, and SPECCTRAQ uest are trademarks of Cadence Design Systems, is a service mark of Cadence Design Systems, other brand and product names mentioned herein are used for identification purposes only and are registered trademarks, trademarks.

2 Or service marks of their respective online edition 31 May 2000 Cadence PCB Systems Division (PSD) officesPSD main office (Portland)(503) 671-9500 PSD Irvine office(949) 788-6080 PSD Japan office81-45-682-5770 PSD UK office44-1256-381-400 PSD customer support(877) 237-4911 PSD web customer support web customer support email PCB Systems Division13221 SW 68th Parkway, Suite 200 ContentsHow to Use This Online ManualHow to print this online manual xiiWelcome xiiiOverview xivTypographical conventions xivCommand syntax formats xvNumeric value conventions xviNumeric expression conventions xviiCommand line options for Orcad applications xxCommand files xxCreating and editing command files xxLog files xxiEditing log files xxiiSimulation command line specification format xxiiiSimulation command line options xxivSpecifying simulation command line options xxvCommandsCommand Reference for PSpice and PSpice A/D (AC analysis).

3 ENDALIASES(aliases and endaliases) (DC analysis) 32 Linear sweep 33 Logarithmic sweep 33 Nested sweep (user-defined distribution) 35 Deriving updated parameter values 35 Usage example (end of circuit) (external port) (Fourier analysis) (function) (initial bias point condition) (include file) (library file) (load bias point file) (Monte Carlo analysis) (model definition) 48 Parameters for setting temperature 51 Model parameters for device temperature 51 Examples 51 Contents4 Special considerations (set approximate node voltage for bias point) (noise analysis) (bias point) (analysis options) 57 Flag options 57 Option with a name as its value 58 Numerical options with their default values 59 Options for scheduling changes to runtime parameters 60 PSpice A/D digital simulation condition messages (parameter) (plot) (print) (Probe) 67DC Sweep and transient analysis output variables 68 Multiple-terminal devices 70AC analysis 72 Noise analysis (save bias point to file) 75 Usage examples (sensitivity analysis) (parametric analysis) 79 Usage examples (stimulus library file) (stimulus) (subcircuit) (end subcircuit) 84 Usage examples (temperature) (text parameter) (transfer) (transient analysis) 90 Scheduling changes to runtime parameters with the.

4 TRAN statement (digital output) (watch analysis results) (sensitivity/worst-case analysis) 95* (comment) 98; (in-line comment) 99+ (line continuation) 100 Differences between PSpice and Berkeley SPICE2 101 Analog devices Analog devices 104 Device types 105 Analog device summary 105 GaAsFET 108 Capture parts 109 Setting operating temperature 109 Model parameters 1105 ContentsGaAsFET model parameters for all levels 110 GaAsFET model parameters specific to model levels 111 Auxiliary model parameters BTRK, DVT, and DVTT 114 GaAsFET equations 115 GaAsFET equations for DC current: all levels 115 GaAsFET equations for DC current: specific to model levels 116 GaAsFET equations for capacitance 121 GaAsFET equations for temperature effect 123 GaAsFET equations for noise 124 References 125 Capacitor 126 Capture parts 127 Breakout parts 127 Capacitor model parameters 128 Capacitor equations 128 Capacitor value formula 128 Capacitor equation for noise 128 Diode 129 Capture parts 130 Setting operating temperature 130 Diode model parameters 131 Diode equations 132 Diode equations for DC current 132 Diode equations for capacitance 132 Diode equations for noise 133 References 133 Diode equations for temperature effects 133 Voltage-controlled voltage source 134 Voltage-controlled current source 134 Basic SPICE polynomial

5 Expressions (POLY) 136 Basic controlled source properties 136 Implementation examples 137 Current-controlled current source 139 Current-controlled voltage source 139 Basic SPICE polynomial expressions (POLY) 139 Independent current source & stimulus 140 Independent voltage source & stimulus 140 Independent current source & stimulus (EXP) 142 Independent current source and stimulus exponential waveform formulas 142 Independent current source & stimulus (PULSE) 143 Independent current source and stimulus pulse waveform formulas 144 Independent current source & stimulus (PWL) 145 Independent current source & stimulus (SFFM) 148 Independent current source & stimulus (SIN) 149 Independent current source and stimulus sinusoidal waveform formulas 150 Junction FET 151 Contents6 Capture parts 152 Setting operating temperature 152 Model parameters 153 JFET equations 154 JFET equations for DC current 155 JFET equations for capacitance 156 JFET equations for temperature effects 157 JFET equations for noise 157 Reference 157 Inductor coupling (and magnetic core) 158 Transmission line coupling 158 Inductor coupling 159 Capture parts 161 Breakout parts 161 Inductor coupling.

6 Jiles-Atherton model 163 Inductor coupling model parameters 163 Including air-gap effects in the inductor coupling model 164 Getting core inductor coupling model values 165 Transmission line coupling 165 Example 166 Lossy lines 166 References 167 Inductor 168 Capture parts 169 Breakout parts 170 Inductor equations 171 Inductance value formula 171 Inductor equation for noise 171 Inductor model parameters 171 MOSFET 172 Capture parts 175 Setting operating temperature 175 MOSFET model parameters 176 For all model levels 176 Model levels 1, 2, and 3 176 Model level 4 176 Model level 5 (EKV version ) 177 Model level 6 (BSIM3 version ) 179 Model level 7 (BSIM3 version ) 179 MOSFET model parameters 182 MOSFET Equations 197 MOSFET equations for DC current 198 MOSFET equations for capacitance 199 MOSFET equations for temperature effects 200 MOSFET equations for noise 201 References 202 Bipolar transistor 203 Capture parts 204 Setting operating temperature 2047 ContentsBipolar transistor model parameters 205 Distribution of the CJC capacitance 207 Bipolar transistor equations 208 Bipolar transistor equations for DC current 209 Bipolar transistor equations for capacitance 210 Bipolar transistor equations for quasi-saturation effect 211 Bipolar transistor equations for temperature effect 212 Bipolar transistor equations for noise 213 References 213 Resistor 214

7 Capture parts 214 Breakout parts 215 Resistor model parameters 216 Resistor equations 217 Resistor value formulas 217 Resistor equation for noise 217 Voltage-controlled switch 218 Capture parts 219 Ideal switches 219 Voltage-controlled switch model parameters 219 Special considerations 219 Voltage-controlled switch equations 220 Voltage-controlled switch equations for switch resistance 221 Voltage-controlled switch equation for noise 221 Transmission line 222 Ideal line 223 Lossy line 224 Capture parts 225 Ideal and lossy transmission lines 225 Coupled transmission lines 226 Simulating coupled lines 227 Simulation considerations 227 Transmission line model parameters 228 References 229 Independent voltage source & stimulus 230 Current-controlled switch 231 Capture parts 232 Ideal switches 232 Current-controlled switch model parameters 233 Special considerations 233 Current-controlled switch equations 233 Current-controlled switch equations for switch resistance 234 Current-controlled switch equation for noise 234 Subcircuit instantiation 235 IGBT 236 Capture parts 237 Setting operating temperature 237 IGBT device parameters 238 IGBT model parameters 239 Contents8 IGBT equations 240 IGBT equations for DC current 241 IGBT equations for capacitance 242 References 243 Digital devicesDigital device summary 252 Digital primitive summary 253 General digital primitive format 256

8 Timing models 258 Treatment of unspecified propagation delays 258 Treatment of unspecified timing constraints 259 Gates 260 Standard gates 261 Standard gate timing model parameters 263 Tristate gates 264 Tristate gate types 265 Tristate gate timing model parameters 266 Bidirectional transfer gates 267 Flip-flops and latches 270 Initialization 270 Timing violations 270 Edge-triggered flip-flops 271 Edge-triggered flip-flop timing model parameters 273 Edge-triggered flip-flop truth tables DFF and JKFF 274 Edge-triggered flip-flop truth tables DFFDE and JKFFDE 275 Gated latch 276 Gated latch truth tables 278 Pullup and pulldown 279 Delay line 280 Programmable logic array 281 Read only memory 285 Random access read-write memory 289 Multi-bit A/D and D/A converter 292 Multi-bit analog-to-digital converter 293 Multi-bit digital-to-analog converter 295 Behavioral primitives 297 Logic expression 298 Pin-to-pin delay 301 Constraint checker 310 Stimulus devices 316 Stimulus generator 317 Time units 318 Stimulus generator examples 319 File stimulus 323 Stimulus file format 323 Transition format 324 File stimulus device 325 Input/output model 3289 ContentsInput/output model parameters 328 Digital/analog interface devices 330 Digital input (N device) 330 Digital input model parameters 331 Digital output (O Device)

9 334 Digital output model parameters 334 Digital model libraries 3387400-series TTL and CMOS library files 3394000-series CMOS library 339 Programmable array logic devices 340 Customizing device equationsIntroduction to Device Equations 342 Making device model changes 343 Changing a parameter name 344 Giving a parameter an alias 344 Adding a parameter 344 Changing the device equations 345 Functional subsections of the device source file 346 Adding a new device 347 Specifying new internal device structure 348 Example 348 Procedure 349 Recompiling and linking the Device Equations option 351 Personalizing your DLL 351 Simulating with the Device Equations option 352 Selecting which models to use from a Device Equations DLL 352 GlossaryIndex10 ContentsHow to Use This Online ManualClick this toolbar button or book


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