REALTEK SINGLE CHIP SINGLE PORT 10/100MBPS FAST …

1 RTL8201(L). REALTEK SINGLE chip . SINGLE PORT 10/100 MBPS. FAST ethernet PHYCEIVER. RTL8201(L). 1. 2 Register 22 PHY 2 .. 16. 2. General Description .. 2 Register 23 Twister_1 .. 16. 3. Block 3 Register 24 Twister_2 .. 16. 4. Pin Assignments .. 4 7. Functional Description .. 17. 5. Pin Description .. 5 MII and Management 17. 100 Mbps MII & PCS Interface .. 5 Auto-negotiation and Parallel Detection .. 18. Serial Network Interface (SNI) .. 5 Flow control support .. 18. Clock Interface .. 5 Hardware Configuration and 19. 100 Mbps Network 6 LED and PHY Address 20. Device Configuration Interface .. 6 Serial Network Interface .. 20. LED Interface/PHY Address 6 Power Down, Link Down, Power Saving, and Isolation Modes 21. Reset and Test 6 Media Interface .. 21. Power and Ground pins .. 6 100 Base Tx/Rx .. 21. 6. Register Descriptions .. 7 10 Base Tx/Rx .. 22. Register 0 Basic Mode Control .. 7 Repeater Mode Operation.

2 22. Register 1 Basic Mode 9 Reset, Power, and Transmit 22. Register 2 PHY Identifier 10 8. Electrical Characteristics .. 23. Register 3 PHY Identifier 10 Characteristics .. 23. Register 4 Auto-negotiation 11 Absolute Maximum Ratings .. 23. Register 5 Auto-Negotiation Link Partner 12 Operating 23. Register 6 Auto-negotiation Expansion (ANER) . 14 Power 23. Register 16 Nway Setup (NSR).. 14 Supply Voltage: Vcc .. 23. Register17 Loopback,Bypass,ReceiverErrorMask(LBREMR ).. 15 Characteristics .. 24. Register 18 RX_ER Counter (REC).. 15 Transmission Without Collision .. 24. Register 19 10 Mbps Network Interface 15 Reception Without 24. Register 20 PHY 15 9. Mechanical Dimensions .. 25. Register 21 PHY 16. 2002-01-18 1 Tel: +49(0)234-9351135 Fax: +49(0)234-9351137 E-MAIL: RTL8201(L). 1. Features The REALTEK RTL8201(L) is a Fast ethernet Phyceiver with MII interface to the MAC chip . It provides the following features: Supports MII interface operation with 5V signal tolerance Supports 10/100 Mbps operation Low operation power consumption Supports half/full duplex operation Adaptive Equalization IEEE compliant 25 MHz crystal/oscillator as clock source Supports IEEE clause 28 auto negotiation Multiple network status LED support Supports power down mode Supports 7-wire SNI (Serial Network Interface).

3 Interface Supports operation under Link Down Power Saving mode Flow control ability support to co-work with Supports repeater mode MAC (by MDC/MDIO). Speed/duplex/auto negotiation adjustable 48-pin LQFP package 2. General Description The RTL8201(L) is a SINGLE -port Phyceiver with an MII (Media Independent Interface). It implements all 10/100M ethernet Physical-layer functions including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10 Base-Tx Encoder/Decoder and Twisted Pair Media Access Unit (TPMAU). It is fabricated with an advanced CMOS process to meet low voltage and low power requirements. The RTL8201(L) can be used as a Network Interface Adapter, MAU, CNR, ACR, ethernet Hub, ethernet Switch. Additionally, it can be used in any embedded system with an ethernet MAC that needs a twisted pair physical connection. 2002-01-18 2 Tel: +49(0)234-9351135 Fax: +49(0)234-9351137 E-MAIL: RTL8201(L).

4 3. Block Diagram 100M. 5B 4B Data Descrambler RXD. MII. Decoder Alignment RXC 25M. Interface 10/100. half/full Switch TXD. 4B 5B. SNI Logic Encoder Scrambler TXC 25M. Interface 10/100M Auto-negotiation Control Logic Link pulse 10M. TXC10. TXD10 Manchester coded 10M Output waveform waveform shaping RXC10. RXD10 Data Recovery Receive low pass filter TXC 25M Parrallel TD+ 3 Level TXO+. TXD to Serial Driver TXO - Variable Current Baseline Peak wander Detect Correction MLT-3 3 Level Adaptive RXIN+. to NRZI Comparator Equalizer RXIN- RXC 25M Serial to ck Slave Master RXD Parrallel data PLL PPL. Control Voltage 25M. 2002-01-18 3 Tel: +49(0)234-9351135 Fax: +49(0)234-9351137 E-MAIL: RTL8201(L). 4. Pin Assignments VCTRL. 36. AVDD1. 32. AVDD0. 31. TPRX+. 28. RTSET. 34. TPTX+. 27. RTT3/. 30. TPRX- 33. TPTX- 35. AGND. 29. AGND. 26. MDIO. 25. MDC. 37. ANE 24. RXER. 38. Duplex 23. CRS. 39. Speed 22. RXDV. 40. RPTR/.

5 RTT2 21. RXD0. 41. LDPS 20. RXD1. 42. RESETB 19. RXD2. 43. ISOLATE. 44. MII/. RTL8201 18. RXD3. SNIB 17. DGND. 45. AGND 16. RXC. 15. LED4/. 46. X1 PAD4. 47. X2 14. DVDD1. 13. LED3/. 48. AVDD2 PAD3. 11. DGND. 8. DVDD0. 10. LED1/. 12. LED2/. PAD1. PAD2. 9. LED0/. PAD0. 2. TXEN. 3. TXD3. 4. TXD2. 5. TXD1. 6. TXD0. 1. COL. 7. TXC. 2002-01-18 4 Tel: +49(0)234-9351135 Fax: +49(0)234-9351137 E-MAIL: RTL8201(L). 5. Pin Description 100 Mbps MII & PCS Interface Symbol Type Pin(s) No. Description TXC O 7 Transmit Clock: This pin provides a continuous clock as a timing reference for TXD[3:0] and TXEN. TXEN I 2 Transmit Enable: The input signal indicates the presence of a valid nibble data on TXD[3:0]. TXD[3:0] I 3, 4, 5, 6 Transmit Data: MAC will source TXD[ ] synchronous with TXC when TXEN is asserted. RXC O 16 Receive Clock: This pin provides a continuous clock reference for RXDV. and RXD[ ] signals. RXC is 25 MHz in the 100 Mbps mode and in the 10 Mbps mode.

6 COL O 1 Collision Detected: COL is asserted high when a collision is detected on the media. CRS I/O 23 Carrier Sense: This pin's signal is asserted high if the media is not in IDEL state. RXDV O 22 Receive Data Valid: This pin's signal is asserted high when received data is present on the RXD[3:0] lines; the signal is deasserted at the end of the packet. The signal is valid on the rising of the RXC. RXD[3:0] O 18, 19, 20, 21 Receive Data: These are the four parallel receive data lines aligned on the nibble boundaries driven synchronously to the RXC for reception by the external physical unit (PHY). RXER O 24 Receive error: if any 5B decode error occurred such as invalid J/K, T/R, invalid symbol, this pin will go high MDC I 25 Management Data Clock: This pin provides a clock synchronous to MDIO, which may be asynchronous to the transmit TXC and receive RXC clocks. MDIO I/O 26 Management Data Input/Output: This pin provides the bi-directional signal used to transfer management information.

7 Serial Network Interface (SNI). 10 Mbps only Symbol Type Pin(s) No. Description COL O 1 Collision Detect RXD0 O 21 Received Serial Data CRS O 23 Carrier Sense RXC O 16 Receive Clock: Resolved from received data TXD0 I 6 Transmit Serial Data TXC O 7 Transmit Clock: Generate by PHY. TXEN I 2 Transmit Enable: For MAC to indicate transmit operation Clock Interface Symbol Type Pin(s) No. Description X2 O 47 25 Mhz Crystal Output: This pin provides the 25 MHz crystal output. X1 I 46 25 Mhz Crystal Input: This pin provides the 25 MHz crystal input. 2002-01-18 5 Tel: +49(0)234-9351135 Fax: +49(0)234-9351137 E-MAIL: RTL8201(L). 100 Mbps Network Interface Symbol Type Pin(s) No. Description TPTX+ O 34 Transmit Output TPTX- O 33. RTSET I 28 Transmit bias resistor connection: This pin should be pulled to GND by a resistor. TPRX+ I 31 Receive input TPRX- I 30. Device Configuration Interface Symbol Type Pin(s) No. Description ISOLATE I 43 Set high to isolate the RTL8201(L) from the MAC.

8 This will also isolate the MDC/MDIO management interface. In this mode, the power consumption is minimum. RPTR/RTT2 I 40 Set high to put the RTL8201(L) into repeater mode. In test mode, this pin is re-defined as RTT2. SPEED I 39 Set high to put the RTL8201(L) into 100 Mbps operation DUPLEX I 38 Set high to enable full duplex ANE I 37 Set high to enable Auto-negotiation mode, set low to force mode LDPS I 41 Set high to put the RTL8201(L) into LDPS mode, MII/SNIB/T I 44 Pull high to set the RTL8201(L) into MII mode operation XD5(test). LED Interface/PHY Address Config Symbol Type Pin(s) No. Description LED0/PAD0 O 9 Link LED. LED1/PAD1 O 10 Full Duplex LED. LED2/PAD2 O 12 Link 10/ACT LED. LED3/PAD3 O 13 Link 100/ACT LED. LED4/PAD4 O 15 Collision LED. Reset and Test pins Symbol Type Pin(s) No. Description RTT3/CTRL O 27 Currently a test pin, this pin may be utilized for future functions. RESETB I 42 RESETB: Setting low to reset the chip .

9 Power and Ground pins Symbol Type Pin(s) No. Description AVDD0 P 32 Analog power: power supply for analog circuit; should be well decoupled AVDD1 P 36 Analog power: power supply for analog circuit; should be well decoupled AVDD2 P 48 power supply for PLL, should be well decoupled and use a bead with 100ohm @ 100 MHz to connect to analog power AGND P 29,35,45 Analog Ground: Should be connected to a larger GND plane DVDD0 P 8 Digital Power: power supply for digital circuit. DVDD1 P 14 Digital Power: power supply for digital circuit. DGND P 11,17 Digital Ground: Should be connected to a larger GND plane 2002-01-18 6 Tel: +49(0)234-9351135 Fax: +49(0)234-9351137 E-MAIL: RTL8201(L). 6. Register Descriptions This section will describe definitions and usage for each of the registers available in the RTL8201. The first six registers of the MII are defined by the MII specification. Other registers are defined by REALTEK Semiconductor Corp.

10 For internal use and are reserved for specific uses. Register Description Default (h). 0 Basic Mode Control Register 3100. 1 Basic Mode Status Register 7849. 2 PHY Identifier 1 Register 0000. 3 PHY Identifier 2 Register 8201. 4 Auto-negotiation Advertisement Register 1E1. 5 Auto-negotiation Link Partner Ability Register 80. 6 Auto-negotiation Expansion Register 0. Register 0 Basic Mode Control Address Name Description/Usage Default/Attribute 0:<15> Reset Reset: This bit sets the status and control registers of the PHY in a 0, RW. default state. In order to reset the RTL8201L by software control, a 1'. must be written to bit 15 using an MII write operation. The bit clears itself after the reset process is complete, and does not need to be cleared using a second MII write. Writes to other Control register bits will have no effect until the reset process is completed, which requires approximately 1us. Writing a 0' to this bit has no effect.