RF Power Amplifiers - MIT OpenCourseWare

1 The World Leader in High-Performance Signal Processing SolutionsRF IFRF Power AmplifiersMay 7, 20032RF IFOutline PA IntroductionzPower transfer characteristicszIntrinsic PA metricszLinear and Non-linear amplifierszPA Architectures Single-Stage Linear PAzLoad-line theoryzTransistors size zInput and Output MatchingzSo why is this so hard? High-efficiency PAszClass A, AB, B and C amplifiers3RF IFOutline (cont.) Real-World Design ExamplezSelecting architecture, number of stageszDesigning stageszTuning: inter-stage match and output System specificationszRuggedness: load mis-match and VSWRzLinearity: spectral mask (ACPR), switching transientszNoise in receive band Power Control4RF IFPA Transfer characteristicsDefining linearity:G01 Pin(dBm)Pout(dBm)Pout= Pin+ Glinearnon-linear (actual)5RF IFPA Transfer characteristicsDefining linearity:Gain (dB)Pin(dBm)Pout(dBm)G-1P1dBPMAX6RF IFPA Introduction: Intrinsic PA Metrics P1dB.

2 Output Power at which linear gain has compressed by 1dB (measure of linear Power handling) PMAX: Maximum output Power (saturated Power ) Gain: Generally taken to mean transducer gain PAE: Power -added EfficiencyPower delivered to loadPower available from sourcePower to load Power from sourcePower from supply7RF IFLinear and Non-linear PAs Linear PA generally refers to a PA which operates at constant gain, needs to preserve amplitude informationPOUT(dBm)PIN(dBm)Designed to operate here Not necessarily class A (will discuss later ..) Peak efficiencies often only 40 to 45 % Useful for modulation schemes with amplitude modulation (QPSK, 8-PSK, QAM)8RF IFLinear and Non-linear PAs Non-linear PA generally refers to a PA designed to operate with constant PIN, output Power varies by changing gainPOUT(dBm)PIN(dBm)Designed to operate here:NOT fixed gain!

3 POUT adjusted throughbias control Operation in saturated mode leads to high peak efficiencies > 50%; backed-off efficiencies drop quickly Useful for constant-envelope modulation schemes (GMSK)9RF IFPA ArchitecturesTypical 2-stage ( ) designVB150 inputVPOS50 Max Power transfer?IREFVB210RF IFPA ArchitecturesTypical 2-stage RF PA designVB1VB250 RF inputVPOS matchingnetworkmatchingnetworkinductive RF chokeallows output to riseabove VPOS, doesn tdissipate powerMay require additionalRF choke here to isolateinput from bias circuit L s and C s to transform loadimpedance11RF IFPA ArchitecturesTypical 2-stage RF PA designVB1VB250 RF inputVPOS matchingnetworkmatchingnetworkAdditional capsmay be required formatching network,harmonic termination12RF IFPA ArchitecturesTypical 2-stage RF PA designVB1VB250 RF inputVPOS matchingnetworkmatchingnetworkbond wires (at least.)

4 13RF IFPA ArchitecturesTypical 2-stage RF PA designVB1VB250 RF inputVPOS matchingnetworkmatchingnetworkConsider this ..14RF IFPA Architectures Gain stage is one transistor with passive elements Active components often limited to 2 or 3 transistors (gain stages) in signal path Transistor design very important!zMany parallel transistors often look like mini-circuits themselves Passive components just as important as transistors!zCircuits must be tunable to account for uncertainties in determining values a priori( simulations stink especially large-signal, RF simulations)zQ and parasitic elements of passives important15RF IFSingle-Stage Linear PA Load-line theory: the maximum Power that a given transistor can deliver is determined by the Power supply voltage and the maximum current of the transistorIDor IC (mA/mm)VDSor VCE(V)2*VPOSIMAXRLOAD,opt.

5 2 VPOS/ IMAX16RF IFSingle-Stage Linear PA Transistor size chosen to deliver required output powerPOUT IMAX VPOS/ 4 IDor IC (mA/mm)VDSor VCE(V)2*VPOSIMAXQ uiescent point:Class AIMAX/2, VPOSRL, IFSingle-Stage, Linear PA Design output match to transform 50 load to RL,optat transistor output; then design input match for gain (complex conjugate)VB150 CJCoutputmatchinputmatchVPOS18RF IFSeems simple, so why is this so hard? Determining IMAXis not so easy zFor BJTs, one reference suggested that the best way of estimating its value is to build an optimized class A amplifier and observe the dc supply current. 1zSomewhat easier for depletion-mode GaAs FETs IMAX often corresponds to VGS = 0 VzValues don t scale linearly with transistor size Optimal load resistance only a theoretical numberzTransmission line effects, parasitic L s and C s significant at RFzCommon practice is to vary the load of an actual transistor to determine the peak output Power : the load-pull measurement(Noticing a distinct pattern of empirical design emerging?)

6 1RF Power Amplifiers for Wireless Communications, Steve Cripps, Artech House, Boston, IFSeems simple, so why is this so hard? Now consider the problem for multiple stages .. double the troublezTypical single-stage gain only 10 15 dBzInter-stage match now required to match input impedance of 2ndstage to desired output impedance of 1ststage. Problems with matching circuits:zLarge matching ratios high Q circuits for simple L matcheszMulti-segment matches use valuable real estate, add cost Transistor itself maters a lot!zMany parallel transistorzBallasting, balancing and layout extremely important 20RF IFHigh-efficiency PAs Input signal swing turns on transistor conduction for only part of sinusoidal periodIDor IC (mA/mm)VDSor VCE(V)IMAXQ uiescent point:Class AB to BClass A21RF IFHigh-Efficiency PAs tIDor ICClass A: 2 3 IDor ICClass AB: t 2 3 IDor ICClass B: t 2 3 Conduction Angle: = 2 < < 2 = Class C: < 22RF IFHigh-Efficiency PAs Assume output match will filter out non-linearities caused by discontinuous conduction:VB150 outputmatchinputmatch50 transformed to RL,opt.

7 All harmonics filtered out23RF IFHigh-Efficiency PAs If all harmonics filtered out, then voltage output at load is a pure sinusoid, despite discontinuous conduction tVOUT 2 3 IC t 2 3 IMAX Energy stored in reactive elements delivers current to the load during transistor off-portion of cycle24RF IFHigh-Efficiency PAs Now consider peak efficienciesCalculate fundamental component of current** There are many texts which cover reduced-conduction angle calculations. See for example PrinciplesOf Power Electronics,Kassakian, Schelcht and Verghese, Ch. t2 /2 Ipk= IMAX IQIMAXIQ(1/2 ) /2 /2IQ+ Ipkcos( t) d tIdc=(1/ ) /2 /2 Ipkcos( t) cos(n t) d tIn=25RF IFHigh-Efficiency PAsFrom phasor plot: cos( /2) = IQ/ Ipk= IQ/ (IMAX IQ) Put it all together and do the math, you get:Assume VOUTthe same for all classes:I1,0-p= sin 1 cos( /2)IMAX2 Idc=2sin( /2) cos( /2)1 cos( /2)IMAX2 V1,0-p= VPOS26RF IFHigh-Efficiency PAs Summary of PA ideal peak efficienciesClass A:(IMAX/2) / 2 VPOS / 2(IMAX /2) VPOSP1 Pdc== 50 %Class B:(IMAX/2) / 2 VPOS / 2(IMAX / ) VPOSP1 Pdc== 78 %Class C.

8 Ideally can go to 100%, but P1drops steadily beyond = , goes to 0 at 100%!27RF IFHigh-Efficiency PAs What happened to our load line? zFor class B fundamental RL,opt= VPOS/(IMAX/2) Didn t changeIDor IC (mA/mm)VDSor VCE(V)IMAXC lass A2 VPOSVPOS?Class B is here!28RF IFHigh-Efficiency PAs What happened to our load line? zFor class B fundamental RL,opt= VPOS/(IMAX/2) Didn t changeIDor IC (mA/mm)VDSor VCE(V)IMAXC lass A2 VPOSVPOSC lass B is here!quasi-staticIn quasi-staticpicture, resistance presented to transistor output cut in half. But average resistance is the same for class AIMAX/229RF IFHigh-Efficiency PAs Now consider linearity zClearly the current waveforms are far from linearBUT.

9 ZOverall POUTvs. PINtransfer function can still be quite linear, especially for true Class B where output current waveform is symmetrical with respect to input waveformIDor IC t 2 3 Because conduction angle is constant,POUT changes proportional to PIN30RF IFReal-World Design Example IDEAL: Design each stage independentlyzDetermine required gain number of stageszDetermine POUTfor each stagezDetermine RL,optfor each stagezDetermine input impedance for each stagezDesign matching networks for inter-stage, load and input REALITY:zIMAX doesn t scale nicely with transistor size. Without good IMAX numbers, can t determine RL,opt.

10 Need to do load pull measurements have limited accuracy for very large transistorszDesigns are very empirically driven!31RF IFReal-World Design ExampleGSM 900 MHz, GaAs HBT PA Design POUT= 33 dBm (linear) = 2 WVCC= VCC2/ 2*POUT= 3 IMAX= 2*VCC/RLOAD= A(Note: expect saturated Power to be ~ 35 dBm) Input Power : constant-envelope +5 dBm Gain = POUT PIN = 27 dB. Expect roughly 10 dB per stage3 STAGE DESIGN32RF IFReal-World Design Example Stage 1: Gain = 10 dB POUT= 15 dBmzRL1= VCC2/ 2*POUT= 194 zIMAX= 2*VCC/RLOAD= 36 mAzChose class A: IDC= IMAX/2 = 18 mA(18 mA insignificant compared to A) Stage 2: Gain = 10 dB POUT= 25 dBmzRL2= zIMAX= 360 mAzStill probably class A (maybe AB): IDC= IMAX/2 = 180 mA Stage 3: Gain = 7 dB POUT= 33 dBmzRL2= 3 , IMAX= AzClass B: IDC= IMAX/ = 742 mA33RF IFReal-World Design ExampleA note on Gain Taking a very simplistic view of common emitter stages:zgm1= IC/ VTh= 18 mA / V = Szgm1RL1= 194 = 135 NOT 10 dB!