RSL10 - Bluetooth 5 Radio System-on-Chip (SoC)

1 RSL10 . Bluetooth ) 5 Radio System-on-Chip (SoC). Introduction RSL10 is an ultra low power, highly flexible multi protocol GHz Radio specifically designed for use in high performance wearable and medical applications. With its Arm Cortex M3 Processor and LPDSP32 DSP core, RSL10 supports Bluetooth low energy technology and GHz proprietary protocol stacks, without sacrificing power consumption. Key Features Rx Sensitivity ( Bluetooth Low Energy Mode, 1 Mbps): 94 dBm WLCSP51. Data Rate: to 2000 kbps CASE 567MT. Transmitting Power: 17 to +6 dBm Peak Rx Current = mA ( V VBAT).

2 Peak Rx Current = mA (3 V VBAT). 1 48. Peak Tx Current (0 dBm) = mA ( V VBAT). QFN48. Peak Tx Current (0 dBm) = mA (3 V VBAT) CASE 485BA. Bluetooth 5 Certified with LE 2M PHY Support Arm Cortex M3 Processor Clocked at up to 48 MHz LPDSP32 for Audio Codec Supply Voltage Range: V RSL10 RSL10 . Current Consumption ( V VBAT): AWLYYWWG AWLYWW. G. Deep Sleep, IO Wake up: 50 nA. Deep Sleep, 8 kB RAM Retention: 300 nA (QFN48) (WLCSP51). Audio Streaming at 7 kHz Audio BW: mA RX, mA TX. Current Consumption (3 V VBAT): XXXXXX. A. = Specific Device Code = Assembly Location Deep Sleep, IO Wake up: 25 nA WL = Wafer Lot Deep Sleep, 8 kB RAM Retention: 100 nA Y or YY = Year Audio Streaming at 7 kHz Audio BW: mA RX, mA TX WW = Work Week G or G.

3 384 kB of Flash Memory = Pb Free Package Highly integrated System on Chip (SoC). Supports FOTA (Firmware Over The Air) Updates ORDERING INFORMATION. Device Package Shipping . NCH RSL10 WLCSP51 5000 / Tape &. 101WC51 ABG (Pb Free) Reel NCH RSL10 QFN48 3000 / Tape &. 101Q48 ABG (Pb Free) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: May, 2018 Rev. 3 RSL10 /D.

4 RSL10 . FEATURES. Arm Cortex M3 Processor: A 32 bit core for Flexible Supply Voltage: RSL10 integrates high . real time applications, specifically developed to enable efficiency power regulators and has a VBAT range of high performance low cost platforms for a broad range to V. See Table 2. RECOMMENDED. of low power applications. OPERATING CONDITIONS. LPDSP32: A 32 bit Dual Harvard DSP core that Highly Configurable Interfaces: I2C, UART, two SPI. efficiently supports audio codecs required for wireless interfaces, PCM interface, multiple GPIOs. It also audio communication.

5 Various codecs are available to supports a digital microphone interface (DMIC) and an customers through libraries that are included in output driver (OD). RSL10 's development tools. The Asynchronous Sample Rate Converter (ASRC). Radio Frequency Front End: Based on a GHz RF Block and Audio Sink Clock Blocks Provides a means transceiver, the RFFE implements the physical layer of of synchronizing the audio sample rate between an the Bluetooth low energy technology standard and other audio source and an audio sink. The audio sink clock proprietary or custom protocols.

6 Also provides a high accuracy mechanism to measure an Protocol Baseband Hardware: Bluetooth 5 certified input clock used for the RTC or protocol timing. and includes support for a 2 Mbps RF link and custom Flexible Clocking Scheme: RSL10 must be clocked protocol options. The RSL10 baseband stack is from the XTAL/PLL of the Radio front end at 48 MHz supplemented by support structures that enable when transmitting or receiving RF traffic. When RSL10 . implementation of ON Semiconductor and customer is not transmitting/receiving RF traffic, it can run off designed custom protocols.

7 The 48 MHz XTAL, the internal RC oscillators, the Highly Integrated SoC: The dual core architecture is 32 kHz oscillator, or an external clock. A low complemented by high efficiency power management frequency RTC clock at 32 kHz can also be used in units, oscillators, flash and RAM memories, a DMA Deep Sleep Mode. It can be sourced from either the controller, along with a full complement of peripherals internal XTAL, the RC oscillator, or a digital input pad. and interfaces. Diverse Memory Architecture: 76 kB of SRAM. Deep Sleep Mode: RSL10 can be put into a Deep program memory and 88 kB of SRAM data memory Sleep Mode when no operations are required.

8 Various are available. A total of 384 kB of flash is available to Deep Sleep Mode configurations are available, store the Bluetooth stack and other applications. The including: Arm Cortex M3 processor can execute from SRAM. IO wake up configuration. The power and/or flash. consumption in deep sleep mode is 50 nA ( V IP Protection Feature: Ensures that the customer's VBAT). flash contents cannot be copied by a third party. It Embedded 32 kHz oscillator running with interrupts prevents any core or memory from being accessed from timer or external pin. The total current drain is externally after the chip has booted.

9 90 nA ( V VBAT). Ultra Low Power Consumption Application As above with 8 kB RAM data retention. The total Examples: current drain is 300 nA ( V VBAT). Audio Signal Streaming: IDD = mA @ VBAT. With the exception of IO wake up only V in Rx Mode for receiving, decoding and configuration, the on chip buck converter can also sending an 7 kHz bandwidth audio signal to the SPI. be enabled to reduce current consumption in Deep interface using a proprietary custom audio protocol Sleep Mode (at higher VBAT voltages). from ON Semiconductor. Standby Mode: Can be used to reduce the average Low Duty Cycle Advertising: IDD mA for power consumption for off duty cycle operation, advertising at all three channels at 5 second intervals ranging typically from a few ms to a few hundreds of @ VBAT 3 V, DCDC converter enabled.

10 Ms. The typical chip power consumption is 30 mA in RoHS Compliant Device Standby Mode. Multi Protocol Support: Using the flexibility provided by LPDSP32, the Arm Cortex M3 processor, and the RF front end; proprietary protocols and other custom protocols are supported. 2. RSL10 . RSL10 INTERNAL BLOCK DIAGRAM. The block diagram of the RSL10 chip is shown in Figure 1. RF. Power Management Radio PHY. Battery Timers Baseband controller DMA Bluetooth 5 (LE 2M) and custom protocol IP Protection LPDSP32 JTAG. XTAL_32 kHz 32 bit Dual Harvard core Oscillators RAMs and XTAL_48 MHz Flash Bus Arm[ Cortex[-M3 SWJ DP.]]