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RSL10 - Bluetooth 5 Radio System-on-Chip (SoC)

DATA Semiconductor Components Industries, LLC, 2016 January, 2022 Rev. 71 Publication Order Number: RSL10 /DBluetooth) RadioSystem-on- chip (SoC) RSL10 IntroductionRSL10 is an ultra low power, highly flexible multi GHz Radio specifically designed for use in high performancewearable and medical applications. With its Arm Cortex M3 Processor and LPDSP32 DSP core, RSL10 supports Bluetooth LowEnergy technology and GHz proprietary protocol stacks, withoutsacrificing power Features Rx Sensitivity ( Bluetooth Low Energy Mode, 1 Mbps): 94 dBm Data Rate: to 2000 kbps Transmitting Power: 17 to +6 dBm Peak Rx Current = mA ( V VBAT) Peak Rx Current = mA (3 V VBAT) Peak Tx Current (0 dBm) = mA ( V VBAT) Peak Tx Current (0 dBm) = mA (3 V VBAT) Bluetooth Certified with LE 2 Mbit PHY (High Speed), as well as Backwards Compatibility and Support for EarlierBluetooth Low Energy Specifications A

(No ext. Balun) Oscillators 32 kHz XTAL 48 MHz XTAL RC Oscillator EXT Clock I/O Bluetooth® Low Energy Radio (Bluetooth5) Arm® Cortex®-M3 processor 32-bit Dual-MAC DSP Core (LPDSP32) Program Memory 384 kB Flash 72 kB RAM 4 kB ROM Data Memory 88 kB RAM DMA AES128Encryption Engine Sample Rate Converter A/D Converter (4 ext. channels) PWM …

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Transcription of RSL10 - Bluetooth 5 Radio System-on-Chip (SoC)

1 DATA Semiconductor Components Industries, LLC, 2016 January, 2022 Rev. 71 Publication Order Number: RSL10 /DBluetooth) RadioSystem-on- chip (SoC) RSL10 IntroductionRSL10 is an ultra low power, highly flexible multi GHz Radio specifically designed for use in high performancewearable and medical applications. With its Arm Cortex M3 Processor and LPDSP32 DSP core, RSL10 supports Bluetooth LowEnergy technology and GHz proprietary protocol stacks, withoutsacrificing power Features Rx Sensitivity ( Bluetooth Low Energy Mode, 1 Mbps): 94 dBm Data Rate: to 2000 kbps Transmitting Power: 17 to +6 dBm Peak Rx Current = mA ( V VBAT) Peak Rx Current = mA (3 V VBAT) Peak Tx Current (0 dBm) = mA ( V VBAT) Peak Tx Current (0 dBm) = mA (3 V VBAT) Bluetooth Certified with LE 2 Mbit PHY (High Speed), as well as Backwards Compatibility and Support for EarlierBluetooth Low Energy Specifications Arm Cortex M3 Processor Clocked at up to 48 MHz LPDSP32 for Audio Codec Supply Voltage Range: V Current Consumption ( V VBAT): Deep Sleep, IO Wake up: 50 nA Deep Sleep, 8 kB RAM Retention: 300 nA Audio Streaming at 7 kHz Audio BW: mA RX, mA TX Current Consumption (3 V VBAT).

2 Deep Sleep, IO Wake up: 25 nA Deep Sleep, 8 kB RAM Retention: 100 nA Audio Streaming at 7 kHz Audio BW: mA RX, mA TX 384 kB of Flash Memory Highly integrated system on chip (SoC) Supports FOTA (Firmware Over The Air) UpdatesWLCSP51 CASE 567 MTXXXXXX = Specific Device CodeA= Assembly LocationWL= Wafer LotY or YY = YearWW= Work WeekG or G= Pb Free PackageRSL10 AWLYYWWGD evicePackageShipping ORDERING INFORMATIONNCH RSL10 101WC51 ABGWLCSP51(Pb Free)5000 / Tape & Reel For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationBrochure, BRD8011 RSL10 101Q48 ABGQFN48(Pb Free)3000 / Tape & Reel481 QFN48 CASE 485BA(QFN48)(WLCSP51)

3 Arm Cortex M3 Processor: A 32 bit core for real timeapplications, specifically developed to enablehigh performance low cost platforms for a broad rangeof low power applications. LPDSP32: A 32 bit Dual Harvard DSP core thatefficiently supports audio codecs required for wirelessaudio communication. Various codecs are available tocustomers through libraries that are included in RSL10 sdevelopment tools. Radio Frequency Front End: Based on a GHz RFtransceiver, the RFFE implements the physical layer ofthe Bluetooth Low Energy technology standard and otherproprietary or custom protocols.

4 Protocol Baseband Hardware: Bluetooth certifiedand includes support for a 2 Mbps RF link and customprotocol options. The RSL10 baseband stack issupplemented by support structures that enableimplementation of onsemi and customer designedcustom protocols. Highly Integrated SoC: The dual core architecture iscomplemented by high efficiency power managementunits, oscillators, flash and RAM memories, a DMAcontroller, along with a full complement of peripheralsand interfaces. Deep Sleep Mode: RSL10 can be put into a Deep SleepMode when no operations are required. Various DeepSleep Mode configurations are available, including: IO wake up configuration.

5 The power consumptionin deep sleep mode is 50 nA ( V VBAT). Embedded 32 kHz oscillator running with interruptsfrom timer or external pin. The total current drain is90 nA ( V VBAT). As above with 8 kB RAM data retention. The totalcurrent drain is 300 nA ( V VBAT). The DC DC converter can be used in buck mode orLDO mode during Sleep Mode, depending on VBAT voltage. Standby Mode: Can be used to reduce the average powerconsumption for off duty cycle operation, rangingtypically from a few ms to a few hundreds of ms. Thetypical chip power consumption is 30 mA in StandbyMode. Multi Protocol Support: Using the flexibility providedby LPDSP32, the Arm Cortex M3 processor, and the RFfront end; proprietary protocols and other customprotocols are supported.

6 Flexible Supply Voltage: RSL10 integrates high efficiency power regulators and has a VBAT range of V. See Table 2. RECOMMENDED OPERATINGCONDITIONS. Highly Configurable Interfaces: I2C, UART, two SPIinterfaces, PCM interface, multiple GPIOs. It alsosupports a digital microphone interface (DMIC) and anoutput driver (OD). The Asynchronous Sample Rate Converter (ASRC)Block and Audio Sink Clock Blocks: Provides a meansof synchronizing the audio sample rate between an audiosource and an audio sink. The audio sink clock alsoprovides a high accuracy mechanism to measure an inputclock used for the RTC or protocol timing.

7 Flexible Clocking Scheme: RSL10 must be clockedfrom the XTAL/PLL of the Radio front end at 48 MHzwhen transmitting or receiving RF traffic. When RSL10is not transmitting/receiving RF traffic, it can run off the48 MHz XTAL, the internal RC oscillators, the 32 kHzoscillator, or an external clock. A low frequency RTCclock at 32 kHz can also be used in Deep Sleep Mode. Itcan be sourced from either the internal XTAL, the RCoscillator, or a digital input pad. Diverse Memory Architecture: 76 kB of SRAM program memory (4 kB of which is PROM containing thechip boot up program, and is thus unavailable to the user)and 88 kB of SRAM data memory are available.

8 A totalof 384 kB of flash is available to store the Bluetooth stackand other applications. The Arm Cortex M3 processorcan execute from SRAM and/or flash. Security: AES128 encryption hardware block for customsecure algorithms and code protection with authenticateddebug port access (JTAG lock ) Ultra Low Power Consumption ApplicationExamples: Audio Signal Streaming: IDD = mA @ V in Rx Mode for receiving, decoding andsending an 7 kHz bandwidth audio signal to the SPIinterface using a proprietary custom audio protocolfrom onsemi. Low Duty Cycle Advertising: IDD foradvertising at all three channels at 5 second intervals@ VBAT 3 V, DCDC converter enabled.

9 RoHS Compliant INTERNAL BLOCK DIAGRAMThe block diagram of the RSL10 chip is shown in Figure 1. RSL10 Block DiagramPower Management UnitDC/DC, LDOA ntennaInterface(No ext. balun )Oscillators32 kHz XTAL48 MHz XTALRC OscillatorEXT Clock I/OBluetooth Low Energy Radio ( Bluetooth )Arm Cortex M3 processor32 bit Dual MAC DSP Core(LPDSP32)Program Memory384 kB Flash72 kB RAM4 kB ROMData Memory88 kB RAMDMAAES128 EncryptionEngineSample Rate ConverterA/D Converter(4 ext. channels)PWM (2x)UARTGPIO (16x)2 wire JTAGW akeup(1x direct, 2x mapped to DIO)DIOI nterfaceSwitchMUXGP Timers(4x, 24bit)SYSTICK TimerSPI (2x) (Master/Slave) I2 CTable 1.

10 ABSOLUTE MAXIMUM RATINGSS ymbolParameterMinMaxUnitVBATP ower Supply Supply Voltage (Note 1) Front end Ground Ground Core and I/O Ground at Any Input PinVSSD + (Note 2)VT storageStorage Temperature Range (Note 3) 40125 CCaution: Class 2 ESD Sensitivity, JESD22 A114 B (2000 V)The QFN package meets 450 V CDM levelStresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be VDDO voltage must not be applied before VBAT voltage on cold Up to a maximum of Applies after soldering to 2.


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