Session at a Glance Tuesday, October 18, 2016

1 Session at a Glance7:00amSession 1 Session 2 Session 3 WLP - 8:00am-10:00am (Oak)3D - 8:00am-10:00am (Pine)Manufacturing - 8:00am-10:00am (Cedar)Fan Out WLP ApplicationsChair: Rey Alvarado, Qualcomm Technologies, : Vivek Dutta, Ormet CircuitsAdvanced Packaging SchemesChair: Herb Reiter, eda 2 asic Consulting, : Amandine Pizzagalli, Yole D veloppementProductivity Solutions IChair: Steffen Kr hnert, NANIUM : Bernard Adams, STATS ChipPAC 8:00amFabrication and Reliability of a Thermally Enhanced WLFO DemonstratorEoin O'Toole, NANIUM Enabled Low-Profile, High Density Fan-Out Wafer-Level PoPMin Tao, , InvensasWafer Level Process Formation of a Polymer Isolated Chip Scale PackageHarry Gee, ON Semiconductor8:30amWafer-Level System in Packaging (SiP) Technologies as 2D, 3D Module/System Integration SolutionJay Kim, nepes CorporationPerformance limits of stacked FO WLPs and their MitigationDev Gupta, , APSTLQ uality Pressures in Advanced PackagingSelim Nahas, Applied Materials; Yao Hong Tan, GLOBALFOUNDRIES; Manan Dedhia, Analog Devices9:00amFOWLP: Comparison & Highlight on the Latest Technologies Trends Romain Fraux, Systems Plus ConsultingSystem-in-Package (SiP) Assembly vs.

2 Solder Paste AttributesSze Pei Lim, Indium CorporationA Practical Approach to Test Through Silicon Vias (TSV)Gerard John, Amkor Technology9:30amSilicon Wafer Integrated Fan-Out Technology (SWIFT)Bora Baloglu, , Amkor TechnologyProcess Controls for Advanced Thermocompression BondingTom Strothmann, Kulicke & SoffaDirect Bond Interconnect (DBI ) Technology as an Alternative to Thermal Compression BondingGuilian Gao, , Invensas Corporation10:00am10:45am11:00am12:00pmS ession 4 Session 5 Session 6 WLP - 1:30pm-3:30pm (Oak)3D - 1:30pm-3:30pm (Pine)Manufacturing - 1:30pm-3:30pm (Cedar)WLP Process DevelopmentsChair: Vivek Dutta, Ormet CircuitsCo-Chair: Rey Alvarado, Qualcomm Technologies, Enablers and ConsiderationsChair: Laurette Nacamulli, Dow Chemical CoCo-Chair: Arun Aiyer, , Anjay TechnologyProductivity Solutions IIChair: Suresh Jayaraman, Amkor TechnologyCo-Chair: Selim Nahas, Applied Materials1:30pmThe Novel Liquid Molding Compound for Fan-Out Wafer-Level Package Katsushi Kan, Nagase ChemteX CorporationHigh Speed Interfaces between Chips Mounted with Different Integration Technologies on an InterposerAndy Heinig, Fraunhofer IIS/EASNew Laser Multi Beam Full Cut Dicing of Wafer-Level Chip-Scale Packages (Fan In)Richard Boulanger , ASMPT ALSI2:00pmDevelopment of Bump Support Film (BSF) for Improving Package Reliability of WLCSP Masanori Yamagishi, Lintec CorporationMiniaturizing RF Module Using Glass Interposer TechnologyGanesh Bhatt, TE ConnectivityRapid Polymer Curing for Improved Manufacturing MetricsJackie Lyn Yusi, Deca Technologies2:30pmElectroplated Nano Twinned Copper for Wafer-Level Package Stream Chung, , Chemleader3D-TSV Assembly: Package Architectures and Trade-offsPaul Silvestri, Amkor TechnologyKey Criteria for Successful Integration of Laser DebondingElizabeth Brandl, EV Group3.

3 00pmFull-field Projection Scanner Patterning Resolution and Overlay PerformanceHabib Hichri, , SUSS MicroTec Photonic Systems Analysis of Die Assembly for and 3D PackagingChet Palesko, SavanSys Solutions LLCW afer-Level Encapsulation-An Alternative Format for Discrete Packaging: Its Challenges and SolutionsEric Kuah, DBA, SM Technology Singapore Pte Ltd3:30pm4:15pm5:30pm-7:00pmNEW! Interactive PresentationsTuesday, October 18, 201610:00am - 1:30pmStudy on a Formulated Flux for Ultra-Fine Flip Chip InterconnectRoderick Chen, SHENMAO America, Inc. Bridging the Gap: A Cohesive Design to Sign-off Platform for Wafer-Level PackagingJohn Ferguson, Mentor GraphicsHigh-Performance, Low-Cost Photoresist Strip for Advanced Packaging ApplicationsGeorge Chiaverini ,Veeco Precision Surface Processing; Amy Lujan, SavanSys Solutions LLCL aminatable Positive-Tone Photosensitive Polyimide Masao Tomikawa, , Toray Industries, Level Reliability of Automotive eWLB (Embedded Wafer-Level BGA)Bernard Adams, STATS ChipPAC BreakExhibit HallPanel Discussion-The Role for Large-Area Panel Processing in the Quest for Low-Cost FOWLPOak Ballroom (2nd Floor)Moderator: Jan Vardaman, TechSearch International, Inc.

4 Chair: John Lannon, , Micross Advanced Interconnect Technology, LLCP anelists: Bernard Adams, STATS ChipPAC Butler, SPTS TechnologiesChoon Lee, Lam ResearchUrmi Ray, Qualcomm Technologies, Inc. Chris Scalan, Deca TechnologiesReception Registration OpensTuesday, October 18, 2016 Refreshment Break & Interactive Presentations (10:00am-1:30pm)Exhibit HallInteractive Presentation Chair: Dale GeeWelcome Comments Oak Ballroom (2nd Floor)Curtis Zwenger, Amkor TechnologyIWLPC General Chair KEYNOTE ADDRESS: Klaus-Dieter Lang, , Fraunhofer IZMA dvanced Technology Platforms for Next Generation of Smart SystemsChair: Curtis Zwenger, Amkor Technology Lunch Break7:00am8:30am9:30amSession 7 Session 8 Session 9 WLP - 10:00am-12:00pm (Oak)3D - 10:00am-12:00pm (Pine)MEMS - 10:00am-12:00pm (Cedar)Fan in & Fan Out Modeling and SimulationsChair: Jie Gong, , KLA-TencorCo-Chair: Luu Nguyen, Texas InstrumentsMetrology and Process ControlChair: Arun Aiyer, , Anjay TechnologyCo-Chair: Tom Strothmann, Kulicke & SoffaMEMS Bonding LandscapeChair: Garrett Oakes, EV GroupCo-Chair: John Lannon, ,Micross Advanced Interconnect Technology, LLC10.

5 00amChip/Package Co-Analysis for Thermal-Induced Stress of Fan-Out Wafer Level PackagingStephen Pan, , ANSYS, of 3D X-Ray Microscopy for 3D IC Process DevelopmentStephen Kelly, ZeissAuSn Eutectic Bonding for Wafer- Level Hermetic Packaging Using a Novel AuSn Patterning ProcessHiroyuki Ishida, SUSS MicroTec KK10:30amSIP Assembly with Sintering Paste in FO-WLPC atherine Shearer, Ormet Circuits, M 3D Metrology for RDL Structures in FO-WLP and Advanced Packaging Using Multi-Sensor Interferometry Moritz Jurgschat, Sentronics Metrology3D Wafer- Level Packaging for MEMS by using a Via Middle Approach based on Copper Through Silicon Vias Together with Copper Thermo-Compression BondingLutz Hofmann, Fraunhofer ENAS11:00amUnderstanding and Solving the Challenges of Chip to Package Co-Design for FOWLPW illiam Acito, Cadence Design SystemsAdvanced Detection and Removal Method of Polymer Residues on Semiconductor SubstratesHelene Richter, , FhG IISB ErlangenAdvances and Applications of Gold Electroplating to Semiconductor DevicesLynne Michaelson, , Technic :30amUltrathin WLFO Eoin O'Toole, NANIUM Thin Substrate Assembly Challenges for Advanced Flip Chip PackageNokibul Islam, STATS ChipPAC WLCSP Technology Solution for Fusion Device of CMOS Integrated Circuit with MEMST akahide Murayama, ULVAC, :00pm1:30pm2:30pmSession 10 Session 11 Session 12 WLP - 3:15pm-5:15pm (Oak)3D - 3:15pm-5:15pm (Pine)MEMS - 3:15pm-5:15pm (Cedar)Fan-Out WLP AdvancesChair: Kevin Demartini, HD MicrosystemsCo-Chair: Jie Gong, KLA-TencorProcessing: Handling, Stacking and BondingChair: Peter Ramm, , Fraunhofer EMFTCo-Chair.

6 Kathy Cook, TesseraMEMS and Sensor Packaging SolutionsChair: John Lannon, , Micross Advanced Interconnect Technology, LLCCo-Chair: Garrett Oakes, EV Group3:15pmDevelopment of High Density Fan-Out Package Platform for High Performance and RF ApplicationsGaurav Sharma, , GLOBALFOUNDRIESLow Cost Electrical Interconnect for 3D Fan-Out Wafer- Level PackagingIvy Qin, , Kulicke & SoffaPatterned Adhesive Transfer for Wafer-Level Packaging ApplicationsElizabeth Brandl, EV Group3:45pmAdvanced Packaging Lithography and Inspection Solutions for Next Generation FOWLP/FOPLP ProcessingKeith Best, Rudolph TechnologiesThin Wafer HandlingTechnologies for TSV PackagingAmandine Pizzagalli, Yole D veloppementWafer-Level Vacuum Packaging of Microbolometer-based Infared ImagersAllan Hilton, RTI International4:15pmHigh Productivity UBM/RDL Deposition by PVD for FOWLP ApplicationsChris Jones, SPTS TechnologiesUltra-thin Gold Passivation as a Viable Alternative for Achieving Low Temperature, Low Pressure Cu-Cu Thermocompression BondingSatish Bonam, , IIT HYDERABADW afer-Level Vacuum-Packaged 2-Axes MEMS Gyroscope with High Yield RateChungMo Yang, , National Nano Fab Center4:45pmAddressing the Needs of RDL/UBM Processing in FOWLPF rantisek Balon, , Evatec AGElectrodeposition of 50 50 m Cu Pillars for 3D Stacking Applications Zaid El-Mekki, imecPhotolithography Alignment Mark Transfer System for Low Cost Advanced Packaging and Bonded Wafer ApplicationsKeith Best, Rudolph Technologies7:30am Registration Opens Workshop#InstructorDay/TimeTopicBeth Keser, Spangler, Microsystems, LLCChet Palesko, SavanSys Solutions LLC and Jan Vardaman, TechSearch International, Inc.

7 John Lau, Pacific TechnologyWS1 Introduction to Fan-Out Wafer-Level Packaging8:30am-12:00pm | DonnerRegistration OpensWednesday, October 19, 2016 KEYNOTE ADDRESS: Rao R. Tummala, , Georgia Institute of TechnologyPromise and Future of Embedding and Fan-Out TechnologiesChair: Chris Scanlan, Deca TechnologiesRefreshment BreakExhibit HallLunch BreakPanel Discussion - Chip-Package Interaction (CPI) Challenges and Solutions for WLP and FOWLPOak Ballroom (2nd Floor)Moderator: Urmi Ray, Qualcomm Technologies, : Curtis Zwenger, Amkor TechnologyPanelists:Paul Silvestri, Amkor TechnologyMark Gerber, ASEPaul Mescher, MicrosoftJan Vardaman, TechSearch International, Nguyen, Texas Instruments Refreshment BreakExhibit HallThursday, October 20, 2016WS2 Wafer-Level Packaging for the Functional Integration of MEMS and ICsWS3 Choosing the Right IC PackagingWS4 Recent Advances and New Trends in Semiconductor Packaging8:30am-12:00pm | Siskiyou1:30pm-5:00pm | Donner1:30pm-5:00pm | Siskiyou