SHARC Processor ADSP-21477/ADSP-21478/ADSP …

1 SHARC and the SHARC logo are registered trademarks of Analog Devices, ProcessorADSP-21477/ADSP-21478/ADSP-2147 9 Rev. DDocument FeedbackInformation furnished by Analog Devices is believed to be accurate and , no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its subject to change without notice. No license is granted by implicationor otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective Technology Way, Box 9106, Norwood, MA 02062-9106 : 2017 Analog Devices, Inc.

2 All rights performance 32-bit/40-bit floating-point Processor optimized for high performance audio processingSingle-instruction, multiple-data (SIMD) computational architectureOn-chip memory up to 5M bits of on-chip RAM, 4M bits of on-chip ROMUp to 300 MHz operating frequencyQualified for automotive applications. See Automotive ProductsCode compatible with all other members of the SHARC familyThe ADSP-2147x processors are available with unique audio-centric peripherals, such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more.

3 Factory programmed ROM versions containing latest audio decoders from Dolby and DTS, available to IP licenses For complete ordering information, see Ordering Guide. Figure 1. Functional Block DiagramInternal Memory I/FBlock 0 RAM/ROMB0D64-BITI nstruction Cache5 Stage SequencerPExPEyPMD 64-BITIOD0 32-BITEPD BUS 64-BITCore BusCross Bar S/PDIFTx/RxPCGA-DDPI Routing/PinsSPI/B UARTB lock 1 RAM/ROMB lock 2 RAMB lock 3 RAMAMISDRAMCTLEPE xternal Port Pin MUXTIMER1-0 SPORT7-0 ASRC3-0 PWM3-0 DAG1/2 CoreTimerPDAP/IDP7-0 TWIIOD0 BUSDTCP/MTMPCGC-DPERIPHERAL BUS 32-BITCOREFLAGS/PWM3-1 JTAGI nternal Memory DMD 64-BITPMD 64-BITCOREFLAGSIOD1 32-BITPERIPHERAL BUSB1D64-BITB2D64-BITB3D64-BITDPI PeripheralsDAI PeripheralsPeripheralsExternal PortSIMD Core STHERMALDIODEFFTFIRIIRMLBSPEP BUSDMD

4 64-BITFLAGx/IRQx/TMREXPWDTRTCSHIFTREGDAI Routing/PinsRev. D|Page 2 of 76|April 2017 ADSP-21477/ADSP-21478/ADSP -21479 TABLE OF CONTENTSG eneral Description .. 3 Family Core Architecture .. 4 Family Peripheral Architecture .. 8I/O Processor Features .. 12 System Design .. 13 Development Tools .. 13 Additional Information .. 15 Related Signal Chains .. 15 Pin Function Descriptions .. 16 Specifications .. 21 Operating Conditions .. 21 Electrical Characteristics .. 22 Maximum Power Dissipation .. 24 Package Information .. 24 ESD Sensitivity .. 24 Absolute Maximum Ratings .. 24 Timing Specifications .. 25 Output Drive Currents.

5 65 Test Conditions .. 65 Capacitive Loading .. 65 Thermal Characteristics .. 6688-LFCSP_VQ Lead Assignment .. 68100-LQFP_EP Lead Assignment .. 70196-BGA Ball Assignment .. 72 Outline Dimensions .. 73 Surface-Mount Design .. 75 Automotive Products .. 75 Ordering Guide .. 76 REVISION HISTORY4/2017 Rev. C to Rev. DChange to RTXI Description in Table 11 of Pin Function Descriptions .. 16 Changes to Operating Conditions .. 21 Change to Figure 5 of Core Clock Requirements .. 25 Changes to AMI Read .. 37 Change to tWDE Switching Characteristic in AMI Write .. 39 Change to Table 64 of Automotive Products .. 75 PRODUCT APPLICATION RESTRICTIONNot for use in in-vivo applications for body fluid constituent monitoring, including monitoring one or more of the compo-nents that form, or may be a part of, or contaminate human blood or other body fluids, such as, but not limited to, car-boxyhemoglobin, methemoglobin total hemoglobin, oxygen saturation, oxygen content, fractional arterial oxygen satura-tion, bilirubin, glucose, drugs, lipids, water, protein, and D|Page 3 of 76|April 2017 GENERAL DESCRIPTIONThe ADSP-2147x SHARC processors are members of the SIMD SHARC family of DSPs that feature Analog Devices Super Harvard Architecture.

6 The processors are source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. These processors are 32-bit/40-bit floating-point processors optimized for high perfor-mance audio applications with a large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI).Table 1 shows performance benchmarks for the ADSP-2147x processors. Table 2 shows the features of the individual product offerings. The diagram on Page 1 shows the two clock domains (core and I/O Processor ) that make up the ADSP-2147x processors.

7 The core clock domain contains the following features. Two processing elements (PEx, PEy), each of which com-prises an ALU, multiplier, shifter, and data register file Two data address generators (DAG1, DAG2) A program sequencer with instruction cache PM and DM buses capable of supporting 2 64-bit data transfers between memory and the core at every core pro-cessor cycle One periodic interval timer with pinout On-chip SRAM (up to 5M bit) A JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user break-points, which allows flexible exception handling. Table 1. Processor BenchmarksBenchmark AlgorithmSpeed (at 300 MHz)Speed (at 200 MHz)1024 Point Complex FFT (Radix 4, with Reversal) sFIR Filter (per Tap)11 Assumes two files in multichannel SIMD ns ns IIR Filter (per Biquad) ns ns Matrix Multiply (Pipelined)[3 3] [3 1][4 4] [4 1] nsDivide (y/ ) ns ns Inverse Square nsTable 2.

8 ADSP-2147x Family FeaturesFeatureADSP-21477 ADSP-21478 ADSP-21479 Frequency200 MHzUp to 300 MHzRAM2M bits3M bits5M bitsROMN/A4M bitsPulse-Width Modulation3 4 units (3 in 100-lead package)External Port Interface (SDRAM, AMI)1 NoYes, 16-BitSerial Ports8 Direct DMA from SPORTs to External MemoryNoYesFIR, IIR, FFT AcceleratorYes MediaLB InterfaceNoAutomotive models onlyWatch Dog Timer2 NoYesReal-Time Clock2, 3 NoYesShift Register2 NoYesIDP/PDAPYesUART1 DAI (SRU)/DPI (SRU2)20/14 PinsS/PDIF Transceiver1 SPI2 TWI1 SRC SNR Performance 128 dBThermal Diode4Ye sVISA SupportYesPackage1100-Lead LQFP88-Lead LFCSP_VQ196-Ball CSP_BGA100-Lead LQFP88-lead LFCSP_VQ1 The 100-lead and 88-lead packages of the processors do not contain an external port.

9 The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function on the 196-ball CSP_BGA package Time Clock (RTC) is supported only for products with a temperature range of 0 C to +70 C and not supported for all other temperature on the 88-lead and 100-lead packages 2. ADSP-2147x Family Features (Continued)FeatureADSP-21477 ADSP-21478 ADSP-21479 Rev. D|Page 4 of 76|April 2017 ADSP-21477/ADSP-21478/ADSP -21479 The block diagram of the ADSP-2147x on Page 1 also shows the peripheral clock domain (also known as the I/O Processor ), which contains the following features: IOD0 (peripheral DMA) and IOD1 (external port DMA) buses for 32-bit data transfers Peripheral and external port buses for core connection External port with an asynchronous memory interface (AMI) and SDRAM controller 4 units for pulse width modulation (PWM) control 1 memory-to-memory (MTM) unit for internal-to-internal memory transfers Digital applications interface that includes four precision clock generators (PCG), an input data port (IDP/PDAP)

10 For serial and parallel interconnect, an S/PDIF receiver/transmitter, four asynchronous sample rate con-verters, eight serial ports, a shift register, and a flexible signal routing unit (DAI SRU). Digital peripheral interface that includes two timers, a 2- wire interface, one UART, two serial peripheral interfaces (SPI), two precision clock generators (PCG), three pulse width modulation (PWM) units, and a flexible signal rout-ing unit (DPI SRU).As shown in the SHARC core block diagram on Page 5, the pro-cessors use two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms.