SINGLE-CHIP 6-PORT 10/100MBPS ETHERNET …

1 RTL8306SD-GR. RTL8306 SDM-GR. RTL8306SD-VC-GR. RTL8306 SDM-VC-GR. RTL8306SD-VT-GR. SINGLE-CHIP 6-PORT 10/100 MBPS. ETHERNET switch controller with . dual MII/RMII INTERFACES. DATASHEET. Rev. 22 June 2007. Track ID: JATR-1076-21. Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047. RTL8306SD/RTL8306 SDM. Datasheet COPYRIGHT. 2007 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. TRADEMARKS. Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners.

2 DISCLAIMER. Realtek provides this document as is , without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. USING THIS DOCUMENT. This document is intended for use by the software engineer when programming for Realtek RTL8306SD/RTL8306 SDM controller chips. Information pertaining to the hardware design of products using these chips is contained in a separate document. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

3 REVISION HISTORY. Revision Release Date Summary 2006/11/24 First release. 2007/06/22 1. Revised Table 1 Pin Assignments Table, page 7 (AI and A0 pin types). 2. Revised Table 5 Port 4 PHY Circuit Interface Pin Definitions, page 16 (Changed DISPORTPRI[4]' to DISPORTPRI[1]' for pin 84 description, and changed DISPORTPRI[4] to DISPORTPRI[0]' for pin 83 description). 3. Revised Table 8 Serial EEPROM and SMI Pins, page 26 (Changed 0 to 25 MHz clock' to 0 to clock' for pin 74 description). 4. Revised Table 9 Strapping Pins, page 27 (changed the strapping pin function description of Pin 111). 5. Revised the MLD description (see section & MLD Snooping Function, page 71). 6. Corrected register names in section Port Mirroring, page 80. 7. Added page selection register description (Table 34 PHY 0 Register 16 (Page 0, 1, 2, 3): Global Control 0, page 91).

4 8. Revised Table 62 DC Characteristics, page 113. 9. Revised Table 65 MII & SMI DC Timing, page 116. 10. Revised section 14 Ordering Information, page 123. 6-PORT 10/100 Mbps SINGLE-CHIP dual MII/RMII switch controller ii Track ID: JATR-1076-21 Rev. RTL8306SD/RTL8306 SDM. Datasheet Table of Contents 1. GENERAL DESCRIPTION ..1. 2. FEATURES ..3. 3. SYSTEM 4. BLOCK DIAGRAM ..5. 5. PIN ASSIGNMENTS ..6. PIN ASSIGNMENTS DIAGRAM ..6. PACKAGE IDENTIFICATION ..6. PIN ASSIGNMENTS TABLE ..7. 6. PIN MEDIA CONNECTION PINS ..9. MODE CONFIGURATION PINS ..9. PORT4 MAC CIRCUIT INTERFACE PORT 4 PHY CIRCUIT INTERFACE PINS ..16. MISCELLANEOUS PINS ..23. PORT LED PINS ..24. SERIAL EEPROM AND SMI PINS ..26. STRAPPING PINS ..27. PORT STATUS STRAPPING PINS ..29. POWER PINS ..31. 7. BASIC FUNCTIONAL switch CORE FUNCTION dual MII/RMII ..32. Port0, 1, 2, 3 Status Flow Control.

5 35. Address Search, Learning, and Aging ..37. Half Duplex Operation ..38. InterFrame Illegal PHYSICAL LAYER FUNCTIONAL OVERVIEW ..39. Auto-Negotiation for UTP ..39. 10 Base-T Transmit Function ..39. 10 Base-T Receive Function ..39. Link 100 Base-TX Transmit 100 Base-TX Receive Power-Down Crossover Detection and Auto Correction ..40. Polarity Detection and Correction ..41. GENERAL FUNCTION OVERVIEW ..42. Reset ..42. Setup and Serial EEPROM Example: 24LC01/02/04 ..44. SMI ..46. Head-Of-Line Blocking ..47. Filtering/Forwarding Reserved Control Frame ..47. Loop Detection ..48. MAC Local Loopback Return to External ..49. 6-PORT 10/100 Mbps SINGLE-CHIP dual MII/RMII switch controller iii Track ID: JATR-1076-21 Rev. RTL8306SD/RTL8306 SDM. Datasheet PHY Digital Loopback Return to Power Generation ..51. Crystal/Oscillator ..51. 8. ADVANCED FUNCTION ACL FUNCTION.

6 52. VLAN FUNCTION ..53. Description ..53. Port-Based VLAN ..55. IEEE Tagged-VID Based VLAN ..56. VLAN Packet Trap to CPU QOS FUNCTION ..59. Bandwidth Control ..59. Priority Assignment ..61. LOOKUP TABLE FUNCTION ..65. Function 4-Way Direct Mapping Algorithm ..65. Lookup and CAM Table Definition ..65. IEEE REMARKING FUNCTION ..66. MIBS MIB Counter Description ..67. MIB Counter Enable/Clear ..68. MIB Counter STORM FILTER FUNCTION ..68. CPU INTERRUPT FUNCTION ..70. IGMP & MLD SNOOPING CPU TAG FUNCTION ..73. IEEE FUNCTION ..75. Port-Based Access MAC-Based Access IEEE FUNCTION ..77. INPUT & OUTPUT DROP FUNCTION ..78. PORT MIRRORING ..80. LED RTL8306SD/RTL8306 SDM Controlling LED ..83. CPU Controlling LED ..84. 9. REGISTER REGISTER LIST ..85. PHY 0 PHY 0 Register 0 (Page 0, 1, 2, 3): PHY 0 Register 1 (Page 0, 1, 2, 3): Status ..88. PHY 0 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1.

7 88. PHY 0 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ..89. PHY 0 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation PHY 0 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner PHY 0 Register 16 (Page 0, 1, 2, 3): Global Control PHY 0 Register 18 (Page 0, 1): Global Control PHY 0 Register 19 (Page 0, 1): Global Control PHY 0 Register 22 (Page 0, 1): Port 0 Control Register PHY 0 Register 24 (Page 0, 1): Port 0 Control Register PHY 1 PHY 1 Register 0 (Page 0, 1, 2, 3): PHY 1 Register 1 (Page 0, 1, 2, 3): Status ..94. 6-PORT 10/100 Mbps SINGLE-CHIP dual MII/RMII switch controller iv Track ID: JATR-1076-21 Rev. RTL8306SD/RTL8306 SDM. Datasheet PHY 1 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ..94. PHY 1 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ..94. PHY 1 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation PHY 1 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner PHY 1 Register 22 (Page 0, 1): Port 1 Control Register PHY 1 Register 24 (Page 0, 1): Port 1 Control Register PHY 2 PHY 2 Register 0 (Page 0, 1, 2, 3): PHY 2 Register 1 (Page 0, 1, 2, 3): Status.

8 96. PHY 2 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ..96. PHY 2 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ..96. PHY 2 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation PHY 2 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner PHY 2 Register 22 (Page 0, 1): Port 1 Control Register PHY 2 Register 23 (Page 0, 1): Global Option Register PHY 2 Register 24 (Page 0,1): Port 2 Control Register PHY 3 PHY 3 Register 0 (Page 0, 1, 2, 3): PHY 3 Register 1 (Page 0, 1, 2, 3): Status ..98. PHY 3 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ..98. PHY 3 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ..98. PHY 3 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation PHY 3 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner PHY 3 Register 16 (Page 0, 1, 2, 3): switch MAC Address ..98. PHY 3 Register 17~18 (Page 0, 1): switch MAC Address.

9 99. PHY 3 Register 22 (Page 0, 1): Port 1 Control Register PHY 3 Register 24 (Page 0, 1): Port 3 Control Register PHY 4 PHY 4 Register 0 (Page 0, 1, 2, 3): PHY 4 Register 1 (Page 0, 1, 2, 3): Status ..100. PHY 4 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ..100. PHY 4 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ..100. PHY 4 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation PHY 4 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner PHY 4 Register 22 (Page 0,1): Port 1 Control Register PHY 4 Register 24 (Page 0, 1): Port 4 Control Register PHY 5 PHY 5 Register 0 (Page 0, 1, 2, 3): PHY 5 Register 1 (Page 0, 1, 2, 3): Status ..103. PHY 5 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ..103. PHY 5 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ..103. PHY 5 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation PHY 5 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner PHY 6 PHY 6 Register 0 (Page 0, 1, 2, 3): PHY 6 Register 1 (Page 0, 1, 2, 3): Status.

10 107. PHY 6 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ..107. PHY 6 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ..107. PHY 6 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation PHY 6 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner PHY 6 Register 22 (Page 0, 1): Port 5 Control Register PHY 6 Register 24 (Page 0, 1): Port 5 Control Register 10. ELECTRICAL CHARACTERISTICS/MAXIMUM RATINGS ..112. 6-PORT 10/100 Mbps SINGLE-CHIP dual MII/RMII switch controller v Track ID: JATR-1076-21 Rev. RTL8306SD/RTL8306 SDM. Datasheet OPERATING RANGE ..112. DC CHARACTERISTICS ..113. AC CHARACTERISTICS ..114. DIGITAL TIMING CHARACTERISTICS ..115. 11. APPLICATION INFORMATION ..118. UTP (10 BASE-T/100 BASE-TX) APPLICATION ..118. 12. DESIGN AND 13. MECHANICAL MECHANICAL DIMENSIONS NOTES ..123. 14. ORDERING INFORMATION ..123. 6-PORT 10/100 Mbps SINGLE-CHIP dual MII/RMII switch controller vi Track ID: JATR-1076-21 Rev.