Single-Lead, Heart Rate Monitor Front End Data Sheet AD8232

1 Single-Lead, Heart Rate Monitor Front End Data Sheet AD8232 Rev. B Document Feedback Information furnished by analog devices is believed to be accurate and reliable. However, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of analog devices . Trademarks and registered trademarks are the property of their respective owners. One Technology Way, Box 9106, Norwood, MA 02062-9106, Tel: 2012 2017 analog devices , Inc. All rights reserved. Technical Support FEATURES Fully integrated single-lead ECG Front end Low supply current: 170 A (typical) Common-mode rejection ratio: 80 dB (dc to 60 Hz) Two or three electrode configurations High signal gain (G = 100) with dc blocking capabilities 2-pole adjustable high-pass filter Accepts up to 300 mV of half cell potential Fast restore feature improves filter settling Uncommitted op amp 3-pole adjustable low-pass filter with adjustable gain Leads off detection: ac or dc options Integrated right leg drive (RLD) amplifier Single-supply operation: V to V Integrated reference buffer generates virtual ground Rail-to-rail output Internal RFI filter 8 kV HBM ESD rating Shutdown pin 20-lead 4 mm 4 mm LFCSP package APPLICATIONS Fitness and activity Heart rate monitors Portable ECG Remote health monitors Gaming peripherals Biopotential signal acquisition FUNCTIONAL BLOCK DIAGRAM Figure 1.

2 GENERAL DESCRIPTION The AD8232 is an integrated signal conditioning block for ECG and other biopotential measurement applications. It is designed to extract, amplify, and filter small biopotential signals in the presence of noisy conditions, such as those created by motion or remote electrode placement. This design allows for an ultralow power analog -to-digital converter (ADC) or an embedded microcontroller to acquire the output signal easily. The AD8232 can implement a two-pole high-pass filter for eliminating motion artifacts and the electrode half-cell potential. This filter is tightly coupled with the instrumentation architec-ture of the amplifier to allow both large gain and high-pass filtering in a single stage, thereby saving space and cost. An uncommitted operational amplifier enables the AD8232 to create a three-pole low-pass filter to remove additional noise. The user can select the frequency cutoff of all filters to suit different types of applications.

3 To improve common-mode rejection of the line frequencies in the system and other undesired interferences, the AD8232 includes an amplifier for driven lead applications, such as right leg drive (RLD). The AD8232 includes a fast restore function that reduces the duration of otherwise long settling tails of the high-pass filters. After an abrupt signal change that rails the amplifier (such as a leads off condition), the AD8232 automatically adjusts to a higher filter cutoff. This feature allows the AD8232 to recover quickly, and therefore, to take valid measurements soon after connecting the electrodes to the subject. The AD8232 is available in a 4 mm 4 mm, 20-lead LFCSP package. Performance is specified from 0 C to 70 C and is operational from 40 C to +85 C. LOD LOD+ AD8232 +VSGNDOUTOPAMP REFOUTOPAMP+SWREFINIAOUTHPSENSEHPDRIVE+I N INRLDRLDFBFRSDNAC/DCLEADS-OFFDETECTION10 k 10k 150k S1S22021341918171615 IAA356789A110A21413121110866-001C2C1AD82 32 Data Sheet Rev.

4 B | Page 2 of 28 TABLE OF CONTENTS Features .. 1 Applications .. 1 Functional Block Diagram .. 1 General Description .. 1 Revision History .. 2 Specifications .. 3 Absolute Maximum Ratings .. 5 ESD Caution .. 5 Pin Configuration and Function Descriptions .. 6 Typical Performance Characteristics .. 7 Instrumentation Amplifier Performance Curves .. 7 Operational Amplifier Performance Curves .. 10 Right Leg Drive (RLD) Amplifier Performance Curves .. 13 Reference Buffer Performance Curves .. 14 System Performance Curves .. 15 Theory of Operation .. 16 Architecture Overview .. 16 Instrumentation Amplifier .. 16 Operational Amplifier .. 16 Right Leg Drive Amplifier .. 17 Reference Buffer .. 17 Fast Restore Circuit .. 17 Leads Off Detection .. 18 Standby Operation .. 19 Input Protection .. 19 Radio Frequency Interference (RFI) .. 20 Power Supply Regulation and Bypassing .. 20 Input Referred Offsets .. 20 Layout Recommendations.

5 20 Applications Information .. 21 Eliminating Electrode 21 High-Pass 21 Low-Pass Filtering and Gain .. 23 Driving analog -to-Digital Converters .. 23 Driven Electrode .. 23 Application Circuits .. 24 Heart Rate Measurement Next to the Heart .. 24 Exercise Application: Heart Rate Measured at the Hands .. 24 Cardiac Monitor Configuration .. 25 Portable Cardiac Monitor with Elimination of Motion Artifacts .. 25 Packaging and Ordering Information .. 27 Outline Dimensions .. 27 Ordering Guide .. 27 REVISION HISTORY 3/2017 Rev. A to Rev. B Updated Outline Dimensions .. 27 Changes to Ordering Guide .. 27 2/2013 Rev. 0 to Rev. A Changes to Table 1 .. 4 Changes to Table 2 .. 6 Change to Figure 17 .. 9 Changes to Figure 22 and Figure 11 Changes to Figure 34 and Figure 14 Changes to Figure 45, Architecture Overview Section, and Instrumentation Amplifier Section .. 17 Changes to Right Leg Drive Amplifier Section, Reference Buffer Section, Fast Restore Circuit Section, and Figure 48; Added Figure 46, Renumbered Sequentially.

6 18 Changes to Figure 49 .. 19 Changes to AC Leads Off Detection Section and Standby Operation 20 Changes to Input Referred Offsets Section .. 21 Changes to Figure 53 and High-Pass Filtering Section .. 22 Changes to Additional High-Pass Filtering Options Section; Added Table 4 .. 23 Changes to Low-Pass Filtering and Gain Section; Added Driving analog -to-Digital Converters Section and Figure 24 Changes to Figure 62, Figure 64, and Heart Rate Measurement Next to the Heart Section .. 25 Changes to Exercise Application: Heart Rate Measured at the Hands and Figure 66 .. 26 Changes to Figure 27 8/2012 Revision 0: Initial Version Data Sheet AD8232 Rev. B | Page 3 of 28 SPECIFICATIONS VS = 3 V, VREF = V, VCM = V, TA = 25 C, FR=low, SDN=high, AC/DC = low, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INSTRUMENTATION AMPLIFIER Common-Mode Rejection Ratio, DC to 60 Hz CMRR VCM = V to V, VDIFF = 0 V 80 86 dB VCM = V to V, VDIFF = V 80 dB Power Supply Rejection Ratio PSRR VS = V to V 76 90 dB Offset Voltage (RTI) VOS Instrumentation Amplifier Inputs 3 8 mV DC Blocking Input1 5 50 V Average Offset Drift Instrumentation Amplifier Inputs 10 V/ C DC Blocking Input1 V/ C Input Bias Current IB 50 200 pA TA = 0 C to 70 C 1 nA Input Offset Current IOS 25 100 pA TA = 0 C to 70 C 1 nA Input Impedance Differential 10|| G ||pF Common Mode 5||15 G ||pF Input Voltage Noise (RTI)

7 Spectral Noise Density f = 1 kHz 100 nV/ Hz Peak-to-Peak Voltage Noise f = Hz to 10 Hz 12 V p-p f = Hz to 40 Hz 14 V p-p Input Voltage Range TA = 0 C to 70 C +VS V DC Differential Input Range VDIFF 300 +300 mV Output Output Swing RL = 50 k +VS V Short-Circuit Current IOUT mA Gain AV 100 V/V Gain Error VDIFF = 0 V % VDIFF = 300 mV to +300 mV 1 % Average Gain Drift TA = 0 C to 70 C 12 ppm/ C Bandwidth BW 2 kHz RFI Filter Cutoff (Each Input) 1 MHz OPERATIONAL AMPLIFIER (A1) Offset Voltage VOS 1 5 mV Average TC TA = 0 C to 70 C 5 V/ C Input Bias Current IB 100 pA TA = 0 C to 70 C 1 nA Input Offset Current IOS 100 pA TA = 0 C to 70 C 1 nA Input Voltage Range +VS V Common-Mode Rejection Ratio CMRR VCM = V to V 100 dB Power Supply Rejection Ratio PSRR 100 dB Large Signal Voltage Gain AVO 110 dB Output Voltage Range RL = 50 k +VS V Short-Circuit Current Limit IOUT 12 mA Gain Bandwidth Product GBP 100 kHz Slew Rate SR V/ s Voltage Noise Density (RTI) en f = 1 kHz 60 nV/ Hz Peak-to-Peak Voltage Noise (RTI) en p-p f = Hz to 10 Hz 6 V p-p f = Hz to 40 Hz 8 V p-p AD8232 Data Sheet Rev.

8 B | Page 4 of 28 Parameter Symbol Test Conditions/Comments Min Typ Max Unit RIGHT LEG DRIVE AMPLIFIER (A2) Output Swing RL = 50 k +VS V Short-Circuit Current IOUT 11 mA Integrator Input Resistor 120 150 180 k Gain Bandwidth Product GDP 100 kHz REFERENCE BUFFER (A3) Offset Error VOS RL > 50 k 1 mV Input Bias Current IB 100 pA Short-Circuit Current Limit IOUT 12 mA Voltage Range RL = 50 k +VS V DC LEADS OFF COMPARATORS Threshold Voltage +VS V Hysteresis 60 mV Propagation Delay s AC LEADS OFF DETECTOR Square Wave Frequency FAC 50 100 175 kHz Square Wave Amplitude IAC 200 nA p-p Impedance Threshold Between +IN and IN 10 20 M Detection Delay 110 s FAST RESTORE CIRCUIT Switches S1 and S2 On Resistance RON 8 10 12 k Off Leakage 100 pA Window Comparator Threshold Voltage From either rail 50 mV Propagation Delay 2 s Switch Timing Characteristics Feedback Recovery Switch On Time tSW1 110 ms Filter Recovery Switch On Time tSW2 55 ms Fast Restore Reset tRST 2 s LOGIC INTERFACE Input Characteristics Input Voltage (AC/DC and FR)

9 Low VIL V High VIH V Input Voltage (SDN) Low VIL V High VIH V Output Characteristics LOD+ and LOD terminals Output Voltage Low VOL V High VOH V SYSTEM SPECIFICATIONS Quiescent Supply Current 170 230 A TA = 0 C to 70 C 210 A Shutdown Current 40 500 nA TA = 0 C to 70 C 100 nA Supply Range V Specified Temperature Range 0 70 C Operational Temperature Range 40 +85 C 1 Offset referred to the input of the instrumentation amplifier inputs. See the Input Referred Offsets section for additional information. Data Sheet AD8232 Rev. B | Page 5 of 28 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage V Output Short-Circuit Current Duration Indefinite Maximum Voltage, Any Terminal1 +VS + V Minimum Voltage, Any Terminal1 V Storage Temperature Range 65 C to +125 C Operating Temperature Range 40 C to +85 C Maximum Junction Temperature 140 C JA Thermal Impedance2 48 C/W JC Thermal Impedance C/W ESD Rating Human Body Model (HBM) 8 kV Charged Device Model (FICDM) kV Machine Model (MM) 200 V 1 This level or the maximum specified supply voltage, whichever is the lesser, indicates the superior voltage limit for any terminal.

10 If input voltages beyond the specified minimum or maximum voltages are expected, place resistors in series with the inputs to limit the current to less than 5 mA. 2 JA is specified for a device in free air on a 4-layer JEDEC board. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION AD8232 Data Sheet Rev. B | Page 6 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 HPDRIVE High-Pass Driver Output. Connect HPDRIVE to the capacitor in the first high-pass filter.