SNUG SILICON VALLEY 2022 AGENDA - vepimg.b8cdn.com

1 SNUG SILICON VALLEY 2022 AGENDA . AT A GLANCE. DAY 1 | MARCH 30, 2022. AND 3D MULTI-DIE ANALOG/MIXED SIGNAL DESIGN AND VERIFICATION DIGITAL DESIGN PHYSICAL VERIFICATION SECURITY, DEFENSE & SILICON TEST AND SUCCESSFUL IP INTEGRATION VERIFICATION HARDWARE VERIFICATION SOFTWARE VERIFICATION SOFTWARE STATIC. AI AND MACHINE LEARNING AUTOMOTIVE LOW POWER SIGNOFF. SYSTEM DESIGN DESIGN AND SIMULATION IN THE CLOUD IMPLEMENTATION CHALLENGES AND SUCCESS AEROSPACE ANALYTICS INTO SOCS ( ,PROTOTYPING) SIMULATION & DEBUG AND FORMAL VERIFICATION. User Presentation: Hide and Seek: Exploring the User Presentation: A Pragmatic Approach to Synopsys Sponsored: Track Keynote: The Frontiers of Hardware Security Using Synopsys High-Accuracy Standard Cell Parasitic Extraction Importance of Optimizing SILICON and Systems by tools. Modeling on Intel 4 technology Leveraging Test to In-Field 8:00 AM 8:50 AM.

2 User Presentation: Efficient Dual Core LockStep Synopsys Sponsored: ESP Power Aware Library Tutorial: Streaming Fabric and Sequential User Presentation: Cryogenically Cooled Electric Processor Design with ASIP Designer: An ST Formal Verification Sign Off with NVIDIA Standard Compression: Breakthrough Test Time and Test Power Train for Electrified Aircraft Propulsion STxP5 Case Study Cell Library Data Reduction KEYNOTE: Catalyze the Impossible 9:00 AM 10:00AM. Dr. Aart de Geus, Synopsys,Inc. Synopsys Sponsored: Fault Injection Verification Synopsys Sponsored: Rapidly Scale and Reduce User Presentation: Once-A-Day Full Chip Physical Synopsys Sponsored: Improving Design User Presentation: Unifying Emulation and FPGA Tutorial: Comprehensive Functional Lint analysis Tutorial: Leveraging Die-to-Die IP to Demystify the Tutorial: DTCO Methodology for improving User Presentation: Security: Next Dimension in Tutorial: A Practical Approach to DFT for Large User Presentation.

3 Demystifying Error Injection in on World's First ASIL D Ready RISC-V Vector Time-to-Market for Your Designs Using Synopsys Verification for Reticle size chips in 7nm using IC Robustness by Addressing Aging Sensitive Paths Build to Meet Hardware and Software Validation Enabling Lowest Noise Leveraging Formal World of 3 DIC Design Routability in Advanced Process Nodes SysMoore complexity for Overall System Design SoCs and AI Architectures UVM Testbench Extension Processor a NSITEXE Case Study Products in Public Cloud Validator and IC Workbench Using STA Aging Solution Needs Technology Tutorial: Design and Verify State-of-the-Art RF ICs Synopsys Sponsored: Low Power Technologies in Tutorial: How New HPC Trends Are 10:00 AM 11:00 AM Using the Synopsys Custom Design Platform RTL2 GDS Flow Influencing High-Speed SerDes IP. Tutorial: Bump Planning Framework For Synopsys Sponsored: Unleashing Cloud's Synopsys Sponsored: Valens' MIPI Automotive Synopsys Sponsored: Simulation Based Standard User Presentation: Full Chip Physical Signoff for User Presentation: ZS4 SoC Digital Twin as a User Presentation: Accurate Aging-Aware User Presentation: Design for Test and ATPG User Presentation: Shift left using Industry's User Presentation: Dynamic MCP (Multi-cycle Tutorial: Ensuring Zero Chip-killing Bugs for Concurrent Design Of C4s And Microbumps In Potential.)

4 Taking Your Chip's Design and Camera IP Use Case Cell Routability Analysis Connectivity and Ultra-high bandwidth Designs Microelectronic Security Research Testbed Robustness with Machine-Learning Speed-up Strategy for a Large ML SoC Fastest Emulator Path) Verification in VCS Complex Designs with Scalable RDC Strategies Intel 3 DIC Foveros based designs Verification to the Cloud 11:00 AM 11:15 AM NETWORKING BREAK. User Presentation: Reduce Physical Signoff Tutorial: Dependable Product Development Life Synopsys Sponsored: Azure HBv3 with AMD User Presentation: Cerebras Achieves 4x Tutorial: Synopsys 3 DIC Multi-die Convergent User Presentation: Automated Register File User Presentation: Emulation Based Power Turn-Around-Time using High Performance Synopsys Sponsored: Track Keynote: Synopsys Sponsored: Accelerating DFT with Tutorial: Using ZeBu Cloud4 for RISC-V SoC User Presentation: Improving SoC Development Tutorial: Achieve Best Efficiency for Static Signoff Cycle for Automotive SoC's in the Context of Milan-X Architectural Advantages for Logic User Presentation.

5 Arm Hierarchical Flow Improvement in Memory/runtime Over Flat Signoff with PrimeTime, StarRC and Tweaker ECO Construction using Synopsys Custom Compiler Analysis Physical Verification with Synopsys IC Validator Manufacturing Next-Generation Microelectronics automated RTL DFT insertion Flow Emulation Flow by Caching EDA Tool Run Results with Multi-mode CDC Analysis Overarching Industry Standards like IEEE PO2851 Simulation Using VCS Analysis using HyperGrid Technology on Amazon Web Services 11:15 AM 12:15 PM Tutorial: HBM3 A Technical Deep Dive User Presentation: P&R Prototype: Dirty Data User Presentation: TestMAX Advisor for Powerful Tutorial: Synopsys Pre- SILICON BSA compliance Tutorial: Build High Quality RTL for Power, Tutorial: Achieving Multi-die and Package Tutorial: Is Your Automotive Reliable? Security is Tutorial: NVIDIA GPUs Enables Faster IC Synopsys Sponsored: RTL-to-Signoff Digital Handling Related to Incomplete RTL and DFT User Presentation: Platform UseCase Peak Power User Presentation: Advances in SILICON Photonics Tutorial: automating Secured SILICON The AISS Tutorial: Enhance Debug Efficiency up to 10X with User Presentation: IR Aware STA and Easy Checking of pipeline and Other Signal Testing and Performance Verification Solution for Placement and Area (PPA) Closure with RTL.

6 Co-design Productivity with 3 DIC Compiler Critical Piece for Safe and Reliable Car Simulations & Signoff Design Solution on Cloud Constraints using Integrated RTLA and TestMAX and Average Power Analysis Using PrimePower Design Enablement with Synopsys Tools Methodology Verdi Intelligent Debug Accelerator (IDX). Connections Arm SoC Architect Advisor 12:15 PM 12:30 PM NETWORKING BREAK. 12:30 PM 1:30 PM. SPOTLIGHT PANELS. The Vision of 1000x Productivity in Analog Designs DA on Cloud: Yesterday's Pipe Dream is Today's Reality Robust PPA for HPC Design Implementation and Signoff 1:30 PM 1:45 PM NETWORKING BREAK. 1:45 PM 2:30 PM The New Dynamism: Women in Engineering and the Vast Opportunity Ahead Synopsys Sponsored: Reduce Physical Signoff Tutorial: Verification and Validation of Automotive Turn-Around-Time Using High Performance User Presentation: Building Source Sync Clocks in Tutorial: Debugging Physical Verification Results: User Presentation: Secure Design and Fabrication: User Presentation: IR Drop Fixing using Timing User Presentation: A Unified Memory BIST.

7 Tutorial: 3 DIC Test and Repair User Presentation: Dynamic IR Drop Analysis Safety SEooC Physical Verification with Synopsys IC Validator System-On-Chip Designs Tips for Smart Debugging A Synopsys-FICS Collaboration ECO Integrated Solution with IR Signoff Tool Diagnostics and Failure Analysis Flow Tutorial: Top Visually-Assisted Layout Automation on Amazon Web Services Tutorial: PCIe : New Features, Security VERIFICATION HARDWARE. 2:30 PM 3:30 PM Features Maximizing Teams' Productivity Options, Emerging Applications Tutorial: Improve Verification Productivity with Tutorial: Automated Method for Obtaining Failure User Presentation: Accelerating Chip Design on VCS Dynamic Test Loading User Presentation: Prioritizing Clock Gating Fixes Tutorial: IC Validator Technology Update: Latest User Presentation: The Role of EDA in Designing User Presentation: Achieving Faster TAT using User Presentation: Design and Implementation of Mode Distribution: A DesignWare ARC Processor Cloud Best Practices for Applying on in a High Performance Design Physical Verification Innovations for Fast Closure for Hardware Security Tweaker Gigachip Hierarchical ECO Functional Protocol-based HSIO Test Solution Case Study Samsung's SAFE Cloud Design Platform (CDP).

8 ENTERTAINMENT & NETWORKING. Tutorial: In-Design Simulation Partial Layout User Presentation: A Case Study for Options to Extraction with Signoff Tools for Samsung User Presentation: Demistifying Secure Design Constraint Asynchronous Timing Paths in the 3:30 PM 4:30PM Foundry Advanced Node STA tool User Presentation: Measuring Crosstalk Pushout Effect using PrimeSim CCK Application DAY 2 | MARCH 31, 2022. AND 3D MULTI-DIE ANALOG/MIXED SIGNAL DESIGN AND VERIFICATION DIGITAL DESIGN PHYSICAL VERIFICATION SECURITY, DEFENSE & SILICON TEST AND SUCCESSFUL IP INTEGRATION VERIFICATION HARDWARE VERIFICATION SOFTWARE VERIFICATION SOFTWARE STATIC. AI AND MACHINE LEARNING AUTOMOTIVE LOW POWER SIGNOFF. YSTEM DESIGN DESIGN AND SIMULATION IN THE CLOUD IMPLEMENTATION CHALLENGES AND SUCCESS AEROSPACE ANALYTICS INTO SOCS ( ,PROTOTYPING) SIMULATION & DEBUG AND FORMAL VERIFICATION.

9 Synopsys Sponsored: TSMC and Synopsys User Presentation: Clock Network Simulation for User Presentation: Enabling Automated Wafer Collaboration on SiliconSmart Library Early Skew & Latency Closure Map Flow with SiliconDash Characterization for Advanced Nodes Synopsys Sponsored: Exploring World of AI- 8:00 AM 8:50 AM Driven Physical Design Applications Tutorial: Accelerate Automotive Software Synopsys Sponsored: Synopsys and Samsung User Presentation: Driving to Entitlement Yield in Development with a Model-Based Approach: An 3nm StarRC Collaboration to Deliver High- Foundry and TI Fabs with Synopsys Yield Explorer Infineon AURIX TC4x Case Study Accuracy QoR for Gate-All-Around Nodes KEYNOTE: AI and Its Impact on Humanity 9:00 AM 9:50 AM. Daniela Rus, MIT. 9:50 AM 10:00 AM NETWORKING BREAK. Tutorial: ASIL D-Compliant SoC Design Synopsys Sponsored: Massive Parallelization in Tutorial: Formally Guaranteeing SoC Connectivity with Synopsys' Safety Specification Format Synopsys Sponsored: Clock Network Simulation Tutorial: Physical Verification for SILICON User Presentation: Implementing HSIO SCAN Test Tutorial: Exploring a Software First Approach to User Presentation: Early Use-cases of VCS ICO.

10 The Cloud: Synopsys Library Characterization on User Presentation: IR-Drop Aware Correctness by Analyzing Impact of Low Power (SSF): Automated End-to-End Traceability, Tutorial: Significantly Improved Coverage and for Early Skew and Latency Closure Photonics Designs with TestMAX ALE on V93000 ATE Avoid SoC Re-spin (Intelligent Coverage Optimization). AWS Logic Insertion Synopsys Sponsored: AI's Next Act Impact on Implementation and Verification Productivity Gain for Analog and Mixed-Signal User Presentation: Library Content Benchmarking Tutorial: AI Accelerators: Edge AI, Cloud AI. 10:00 AM 11:00 AM Chip Design Today and Vision for Future Designs using Industry's First End-to-End Unified and Feature Richness for Better Design PPA and On Premises AI. Reliability Workflow Synopsys Sponsored: Physical Design Hand Book User Presentation: In-System Automotive Test Synopsys Sponsored: Synopsys Defense in Depth User Presentation: ICV LVS Explorer for 2x faster User Presentation: Using PrimeShield Vt-Skew User Presentation: How to Leverage AI to Tutorial: Systems Emulation and Validation with User Presentation: Reactive Sequence User Presentation: Applying Formal Analysis in for Complex Low Power Architecture using Fusion Solution for External Memories Cloud Security Approach and Case Study PDV of High Performance Designs Feature for Corner Reduction Outperform the Competition ZeBu Memory Transactors Methodologies with Multiple Drivers Simulation-based Methodology Compiler 11:00 AM 11:15 AM BREAK.