System on Chip Design and Modelling - University of …

1 System on ChipDesign and ModellingUniversity of CambridgeComputer LaboratoryLecture NotesDr. David J Greaves(C) 2011 All Rights Reserved IIComputer Science TriposEaster Term SOC Design : 2010/11: 12 LECTURES TO CST IICST-II SoC D/M Lecture Notes 2010/11 (1) Register Transfer Language (RTL) (4) Folding, Retiming & Recoding (5) Protocol and Interface (6) SystemC Components (7) Basic SoC Components (9) ESL: Electronic System Level Modelling (10) Transactional Level Modelling (TLM) (11) ABD - Assertion-Based Design (12) Network On chip and Bus Structures. (13) SoC Engineering and Associated Tools (14) Architectural Design Exploration (16) High-level Design Capture and Design : 2010/11: 12 Lectures to CST IIA current-day System on a chip (SoC) consists of several different microprocessor subsystems together withmemories and I/O interfaces.

2 This course covers SoC Design and Modelling techniques with emphasis onarchitectural exploration, assertion-driven Design and the concurrent development of hardware and embeddedsoftware. This is the front end of the Design automation tool chain. (Back end material, such as Design ofindividual gates, layout, routing and fabrication of silicon chips is not covered.)A percentage of each lecture is used to develop a running example. Over the course of the lectures, the exampleevolves into a System On chip demonstrator with CPU and bus models, device models and device drivers.

3 Allcode and tools are available online so the examples can be reproduced and exercises undertaken. The mainlanguages used are Verilog and C++ using the SystemC Groups and Syllabus: Verilog RTL Design with simulation with and without delta cycles, ba-sics of synthesis to gates algorithm and Design examples. Structural hazards, pipelining, memories andmultipliers. SystemC major components of the SystemC C++ class library for hardware modellingare covered with code fragments and demonstrations. Basic SoC Components and Bus , RAM, Timers, DMA, GPIO, Network, Busstructure.

4 Interrupts, DMA and device drivers. Examples. Basic bus bridging. ESL + Transactional systems level (ESL) Design . Architectural Modelling methods. Blocking and non-blocking transaction styles. Approximate and loosetiming styles. Queue and contention Modelling . Examples. ABD: Assertions and of assertion (imperative, safety, liveness, data conservation).Assertion-based Design (ABD). PSL/SVA assertions. Temporal logic compilation of fragments to moni-toring FSM. Further Bus used in today s SoCs (OPB/BVCI, AHB and AXI). Glue logic syn-thesis. Transactor synthesis. Pipeline Tolerance.

5 Network on Term 20111 System -On- chip RECOMMENDED READING Engineering Aspects: FPGA and ASIC Design libraries. Market breakdown: CPU/Commodity/ASIC/FPGA. Further tools used for Design of FPGA and ASIC (timing and power Modelling , place androute, memory generators, power gating, clock tree, self-test and scan insertion). Dynamic frequency andvoltage scaling. Future approachesOnly presented if time permits. developments: BlueSpec,IP-XACT, Kiwi, Custom processor addition to these topics, the running example will demonstrate a few practical aspects of device bus interfacedesign, on chip communication and device control software.

6 Students are encouraged to try out and expand theexamples in their own ReadingSubscribe for webcasts from Design And Reuse : tutorials and whitepapers. Download from OSCI or copy from course , F. (2006).Transaction-level modeling with SystemC: TLM concepts and applications for embeddedsystems. , C. & Fisman, D. (2006).A practical introduction to PSL. Springer (Series on Integrated Circuits andSystems).Foster, & Krolnik, (2008).Creating assertion-based IP. Springer (Series on Integrated Circuits andSystems).Grotker, T., Liao, S., Martin, G. & Swan, S. (2002). System Design with SystemC.

7 Springer. Wolf, W. (2002).Modern VLSI Design ( System -on- chip Design ). Pearson Education. : What is a SoC ?Figure 1: Block diagram of a multi-core platform chip , used in a number of networking System On A chip : typically uses 70 to 140 mm2of SoC is a complete System on a chip . A System includes a microprocessor, memory and peripherals. Theprocessor may be a custom or standard microprocessor, or it could be a specialised media processor for sound,Easter Term 20112 System -On- chip Design FLOW modem or video applications. There may be multiple processors and also other generators of bus cycles, such asDMA controllers.

8 DMA controllers can be arbitrarily complex, and are really only distinguished from processorsby their complete or partial lack of instruction are interconnected using a variety of mechanisms, including shared memories and message-passinghardware entities such as specialised channels and are found in every consumer product, from modems, mobile phones, DVD players, televisions and FlowDesign flow is divided by theStructural RTLlevel into: Front End: specify, explore, Design , capture, synthesise Structural RTL Back End:Structural RTL place, route, mask making, 2 shows a typical Design and maufacturing flow that leads from Design capture to SoC Front EndThe Design must be specified in terms of high-level requirements, such as function, throughput and capture: it is transferred from the marketing person s mind, back of envelope or or wordprocessordocument into machine-readable exploration will try different combinations of processors, memories and bus structures to find animplementation with good power and load balancing.

9 A loosely-timed high-level model is sufficient to computethe performance of an Design will select IP (interlectual property) providers for all of the functional blocks, or else they willexist from previous in-house designs and can be used without license fees, or else freshly synthesis will convert from behavioural RTL to structural RTL. Synthesis from formal high-level forms,including C,C++, SysML statecharts, formal specifications of interfaces and behaviour is beginning to be set simulators (ISS) for embedded processors are needed: purchased from third parties such as ARMand MIPS, or as a by-product of custom processor interface specifications (register maps and other APIs) between components need to be stored.

10 The IP-XACT format may be models that are never intended to be synthesisable and test bench components will also be coded,typically using Back EndAfter RTL synthesis using a target technology library, we have a structural netlist that has no gate and route gives 2-D co-ordinates to each component, adds external I/O pads and puts wiring between thecomponents. RTL annotated with actual implementation gate delays gives a precise power and performancemodel. If performance is not up to par, Design changes are Term 20113 System -On- chip LEVELS OF Modelling ABSTRACTIONF abrication of masks is commonly the most expensive single step ( one million pounds), so must be correctfirst is performed in-house by certain large companies ( Intel, Samsung) but most companies usefoundaries (UMC, TSMC).