Technical Reference Manual - Espressif

1 ESP32 Technical Reference ManualVersion SystemsCopyright This ManualTheESP32 Technical Reference Manualis addressed to application developers. The Manual provides detailedand complete information on how to use the ESP32 memory and pin definition, electrical characteristics, and package information, please seeESP32 UpdatesPlease always refer to the latest version HistoryFor any changes to this document over time, please refer to thelast Change NotificationEspressif provides email notifications to keep customers updated on changes to Technical documentation . Pleasesubscribe certificates for Espressif products System and Functional Address Embedded Internal ROM Internal ROM Internal SRAM Internal SRAM Internal SRAM RTC FAST RTC SLOW External Asymmetric PID Controller Non-Contiguous Peripheral Memory Memory Speed332 Interrupt Matrix (INTERRUPT) Functional Peripheral Interrupt CPU Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU NMI Interrupt Query Current Interrupt Status of Peripheral Interrupt Registers383 Reset and System Reset System Clock CPU Peripheral APB_CLK Source42 Espressif Systems3 Submit documentation FeedbackESP32 TRM (Version ) REF_TICK LEDC_SCLK APLL_SCLK PLL_D2_CLK Clock Source Wi-Fi BT RTC Audio PLL444 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

2 Peripheral Input via GPIO Functional Simple GPIO Peripheral Output via GPIO Functional Simple GPIO Direct I/O via Functional RTC IO_MUX for Low Power and Analog Functional Light-sleep Mode Pin Pad Hold I/O Pad Power VDD_SDIO Power Peripheral Signal IO_MUX Pad RTC_MUX Pin Register GPIO Matrix Register IO MUX Register RTC IO MUX Register GPIO Matrix IO MUX RTC IO MUX Registers735 DPort Functional System and Memory Register87 Espressif Systems4 Submit documentation FeedbackESP32 TRM (Version ) Reset and Clock Interrupt Matrix DMA MPU/MMU APP_CPU Controller Peripheral Clock Gating and Register Registers966 DMA Controller (DMA) Functional DMA Engine Linked UART DMA (UDMA) SPI DMA I2S DMA Interface1167 SPI Controller (SPI) SPI GP-SPI Four-line Full-duplex GP-SPI Four-line Half-duplex GP-SPI Three-line Half-duplex GP-SPI Data GP-SPI Clock GP-SPI Clock Polarity (CPOL) and Clock Phase (CPHA) GP-SPI Parallel Communication Format of Parallel GP-SPI Interrupt SPI DMA Register Registers1288 SDIO Slave Functional SDIO Slave Block Sending and Receiving Data on SDIO Register DMA152 Espressif Systems5 Submit documentation FeedbackESP32 TRM (Version )

3 Packet-Sending/-Receiving Sending Packets to SDIO Receiving Packets from SDIO SDIO Bus Host Slave Register SLC SLC Host HINF Registers1829 SD/MMC Host SD/MMC External Interface Functional SD/MMC Host Controller Command Data Data Transmit Data Receive Software Restrictions for Proper CIU RAM for Receiving and Sending Transmit RAM Receive RAM Descriptor The Structure of a Linked DMAC DMAC Transmission DMAC Reception Clock Phase Register Registers19510 Ethernet Media Access Controller (MAC) Transmit Transmit Flow Retransmission During a Receive Operation216 Espressif Systems6 Submit documentation FeedbackESP32 TRM (Version ) Reception Receive Frame Receive Flow Reception of Multiple Error Receive Status MAC Interrupt MAC Address Unicast Destination Address Multicast Destination Address Broadcast Address Unicast Source Address Inverse Filtering Good Transmitted Frames and Received EMAC_MTL (MAC Transaction Layer) PHY MII (Media Independent Interface) Interface Signals Between MII and MII RMII (Reduced Media-Independent Interface) RMII Interface Signal RMII Station Management Agent (SMA) RMII Ethernet DMA Linked List Transmit Receive Register Registers24011 I2C Controller (I2C) Functional I2C Bus I2C cmd I2C Master Writes to Master Reads from Register Registers29112 I2S Controller (I2S)302 Espressif Systems7 Submit documentation FeedbackESP32 TRM (Version )

4 The Clock of I2S I2S Supported Audio Philips MSB Alignment PCM Module FIFO Sending Receiving I2S Master/Slave I2S Camera-LCD LCD Master Transmitting Camera Slave Receiving ADC/DAC I2S FIFO DMA Register Registers31813 UART Controller (UART) UART Functional UART UART Baud Rate UART Data Flow Hardware Flow Software Flow UART UART UHCI Register UART UHCI Registers34614 LED PWM Controller (LEDC) Introduction378 Espressif Systems8 Submit documentation FeedbackESP32 TRM (Version ) Functional Register Registers38415 Remote Control Peripheral (RMT) Functional RMT RMT Register Registers39716 Motor Control PWM (PWM) Prescaler Timer Operator Fault Detection Capture PWM Timer Configurations of the PWM Timer PWM Timer s Working Modes and Timing Event PWM Timer Shadow PWM Timer Synchronization and Phase PWM Operator PWM Generator Dead Time Generator PWM Carrier Fault Handler Capture Capture Capture Register Registers438 Espressif Systems9 Submit documentation FeedbackESP32 TRM (Version )Contents17 Pulse Count Controller (PCNT) Functional Counter Channel Register Registers48918 Timer Group (TIMG) Functional 16-bit 64-bit Time-base Alarm Register Registers49719 Watchdog Timers (WDT)

5 Functional Operating Write Flash Boot Registers50620 eFuse Functional System Parameter System Parameter System Parameter Programming of System Software Reading of System The Use of System Parameters by Hardware Register Summary515 Espressif Systems10 Submit documentation FeedbackESP32 TRM (Version ) Registers51821 Two wire Automotive Interface (TWAI) Functional TWAI TWAI Data Frames and Remote Error and Overload Interframe TWAI Error Error Error TWAI Bit Nominal Hard Synchronization and Architectural Registers Bit Stream Error Management Bit Timing Acceptance Receive Functional Reset Operation Bit Interrupt Receive Interrupt (RXI) Transmit Interrupt (TXI) Error Warning Interrupt (EWI) Data Overrun Interrupt (DOI) Error Passive Interrupt (TXI) Arbitration Lost Interrupt (ALI) Bus Error Interrupt (BEI) Transmit and Receive Overview of Frame Frame Frame Receive FIFO and Data Acceptance Single Filter Mode547 Espressif Systems11 Submit documentation FeedbackESP32 TRM (Version ) Dual FIlter Error Error Warning Error Bus-Off and Bus-Off Error Code Arbitration Lost Register Registers55422 AES Accelerator (AES) Functional AES Algorithm Key, Plaintext and Encryption and Decryption Register Registers57123 SHA Accelerator (SHA) Functional Padding and Parsing the Message Hash Register Registers57624 RSA Accelerator (RSA) Functional Large Number Modular Large Number Modular Large Number Register Registers58625 Random Number Generator (RNG)

6 Introduction588 Espressif Systems12 Submit documentation FeedbackESP32 TRM (Version ) Functional Programming Register Register58926 External Memory Encryption and Decryption (FLASH) Functional Key Flash Encryption Flash Decryption Register Register59427 MemoryManagementandProtectionUnits(MMU,M PU) Functional PID Embedded External Peripheral60828 Process ID Controller (PID) Functional Interrupt Information Proactive Process Register Registers61529 On Chip Sensors and Analog Signal Capacitive Touch Available Functional Touch SAR Introduction621 Espressif Systems13 Submit documentation FeedbackESP32 TRM (Version ) Outline of RTC SAR ADC DIG SAR ADC Hall Functional Cosine Waveform DMA Register Advanced Peripheral RTC Advanced Peripheral RTC I/O64630 ULP Coprocessor (ULP) Functional Instruction ALU - Perform Arithmetic/Logic Operations Among Operations with Immediate Operations with Stage Count ST Store Data in LD Load Data from JUMP Jump to an Absolute JUMPR Jump to a Relative Offset (Conditional upon R0) JUMPS Jump to a Relative Address (Conditional upon Stage Count Register) HALT End the WAKE Wake up the Sleep Set the ULP Timer s Wake-up Wait for a Number of Take Measurement with Read/Write I Read from Peripheral Write to Peripheral ULP Program Execution657 Espressif Systems14 Submit documentation FeedbackESP32 TRM (Version )

7 RTC_I2C Configuring Using I2C_RD - Read a Single I2C_WR - Write a Single Detecting Error Connecting I C Register SENS_ULP Address RTC_I2C Address SENS_ULP Address RTC_I2C Address Space66531 Low Power Management (RTC_CNTL) Functional Digital Core Voltage Low-Power Voltage Flash Voltage Brownout RTC Low-Power Power-Gating Predefined Power Register Registers684 Glossary710 Abbreviations for Peripherals710 Abbreviations for Registers710 Revision History711 Espressif Systems15 Submit documentation FeedbackESP32 TRM (Version )List of TablesList of Tables1 Address Mapping262 Embedded Memory Address Mapping273 Module with DMA294 External Memory Address Mapping295 Cache memory mode306 Peripheral Address Mapping317 PRO_CPU, APP_CPU Interrupt Configuration358 CPU Interrupts379 PRO_CPU and APP_CPU Reset Reason Values3910 CPU_CLK Source4111 CPU_CLK Derivation4112 Peripheral Clock Usage4213 APB_CLK Derivation4214 REF_TICK Derivation4315 LEDC_SCLK Derivation4316 IO_MUX Light-sleep Pin Function Registers5017 GPIO Matrix Peripheral Signals5218 IO_MUX Pad Summary5719 RTC_MUX Pin Summary5825 Mapping Between SPI Bus Signals and Pin Function Signals11726 Command Definitions Supported by GP-SPI Slave in Half-duplex Mode11927 Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master12128 Clock Polarity and Phase.

8 And Corresponding SPI Register Values for SPI Slave12133 SD/MMC Signal Description18434 DES018935 DES119036 DES219137 DES319139 Destination Address Filtering22040 Source Address Filtering22041 Timing Parameters - Receiving Data22542 Timing Parameters Transmitting Data22643 Transmit Descriptor 0 (TDES0)22744 Transmit Descriptor 1 (TDES1)23145 Transmit Descriptor 2 (TDES2)23146 Transmit Descriptor 3 (TDES3)23147 Transmit Descriptor 6 (TDES6)23148 Transmit Descriptor 7 (TDES7)23249 Receive Descriptor 0 (RDES0)23250 Receive Descriptor 1 (RDES1)23551 Receive Descriptor 2 (RDES2)23552 Receive Descriptor 3 (RDES3)23553 Receive Descriptor 4 (RDES4)236 Espressif Systems16 Submit documentation FeedbackESP32 TRM (Version )List of Tables54 Receive Descriptor 6 (RDES6)23755 Receive Descriptor 7 (RDES7)23757 SCL Frequency Configuration28059 I2S Signal Bus Description30360 Register Configuration30761 Send Channel Mode30762 Modes of Writing Received Data into FIFO and the Corresponding Register Configuration30963 The Register Configuration to Which the Four Modes Correspond30964 Upsampling Rate Configuration31165 Down-sampling Configuration31269 Commonly-used Frequencies and Resolutions37972 Configuration Parameters of the Operator Submodule40773 Timing Events Used in PWM Generator41574 Timing Events Priority When PWM Timer Increments41675 Timing Events Priority when PWM Timer Decrements41676 Dead Time Generator Switches Control Registers42677 Typical Dead Time Generator Operating Modes42782 System Parameters50783 BLOCK1/2/3 Encoding51084 Program Registers51185 Timing Configuration51386 Software Read Registers51488 Data Frames and

9 Remote Frames in SFF and EFF53289 Error Frame53390 Overload Frame53491 Interframe Space53492 Segments of a Nominal Bit Time53793 Bit Information of TWAI_CLOCK_DIVIDER_REG; TWAI Address 0x1854194 Bit Information of TWAI_BUS_TIMING_1_REG; TWAI Address 0x1c54295 Buffer Layout for Standard Frame Format and Extended Frame Format54496 TX/RX Frame Information (SFF/EFF) TWAI Address 0x4054597 TX/RX Identifier 1 (SFF); TWAI Address 0x4454598 TX/RX Identifier 2 (SFF); TWAI Address 0x4854699 TX/RX Identifier 1 (EFF); TWAI Address 0x44546100 TX/RX Identifier 2 (EFF); TWAI Address 0x48546101 TX/RX Identifier 3 (EFF); TWAI Address 0x4c546102 TX/RX Identifier 4 (EFF); TWAI Address 0x50546103 Bit Information of TWAI_ERR_CODE_CAP_REG; TWAI Address 0x30551104 Bit Information of Bits - Bit Information of TWAI_ARB LOST CAP_REG; TWAI Address 0x2c552107 Operation Mode567108 AES Text Endianness568109 AES-128 Key Endianness569110 AES-192 Key Endianness569111 AES-256 Key Endianness569117 MPU and MMU Structur