UDA1334ATS Low power audio DAC with PLL - NXP

1 DATA SHEETP roduct specificationSupersedes data of 2000 Feb 092000 Jul 31 INTEGRATED CIRCUITS UDA1334 ATSLow power audio DAC with PLL2000 Jul 312 NXP SemiconductorsProduct specificationLow power audio DAC with format data digital audio system clock generation2 APPLICATIONS3 GENERAL DESCRIPTION4 ORDERING INFORMATION5 QUICK REFERENCE DATA6 BLOCK DIAGRAM7 PINNING8 FUNCTIONAL stream interface format control9 LIMITING VALUES10 HANDLING11 THERMAL CHARACTERISTICS12 QUALITY SPECIFICATION13DC CHARACTERISTICS14AC INFORMATION16 PACKAGE to soldering surface mount of surface mount IC packages for wave and reflow soldering methods18 DATA SHEET STATUS19 DISCLAIMERS2000 Jul 313 NXP SemiconductorsProduct specificationLow power audio DAC with to V power supply voltage On-board PLL to generate the internal system clock: Operates as an asynchronous DAC, regenerating the internal clock from the WS signal (called audio mode) Generates audio related system clock (output) based on 32, 48 or 96 kHz sampling frequency (called video mode).

2 Integrated digital filter plus DAC Supports sample frequencies from 16 to 100 kHz in asynchronous DAC mode No analog post filtering required for DAC Easy application SSOP16 format data interface I2S-bus and LSB-justified format compatible 1fs input data digital features Digital de-emphasis for kHz sampling frequency Mute audio configuration High linearity, wide dynamic range and low system clock generation Integrated low jitter PLL for use in applications in which there is digital audio data present but the system cannot provide an audio related system clock. This mode is called audio mode. The PLL can generate 256 48 kHz and 384 48 kHz from a 27 MHz input clock. This mode is called video audio DAC is excellently suitable for digital audio portable application, specially in applications in which an audio related system clock is not DESCRIPTIONThe UDA1334 ATS is a single chip 2 channel digital-to-analog converter employing bitstream conversion techniques, including an on-board PLL.

3 The extremely low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low- power portable digital audio equipment which incorporates a playback UDA1334 ATS supports the I2S-bus data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 20 and 24 UDA1334 ATS has basic features such as de-emphasis ( kHz sampling frequency, only supported in audio mode) and INFORMATIONTYPE NUMBERPACKAGENAMEDESCRIPTIONVERSIONUDA13 34 ATSSSOP16plastic shrink small outline package; 16 leads; body width mmSOT369-12000 Jul 314 NXP SemiconductorsProduct specificationLow power audio DAC with PLLUDA1334 ATS5 QUICK REFERENCE DATANote1. The output voltage of the DAC scales proportionally to the power supply analog supply supply analog supply currentaudio mode mAvideo mode mAIDDD digital supply currentaudio mode mAvideo mode mATambambient temperature 40 +85 CDigital-to-analog converter (VDDA=VDDD= )Vo(rms)output voltage (RMS value)at 0 dB (FS) digital input; note 1 900 mV(THD+N)/Stotal harmonic distortion-plus-noise to signal ratiofs= kHz; at 0 dB 90 dBfs= kHz; at 60 dB; A-weighted 40 dBfs=96kHz; at 0dB 85 dBfs=96kHz; at 60 dB; A-weighted 38 dBS/Nsignal-to-noise ratiofs= kHz; code = 0; A-weighted 100 dBfs=96kHz; code=0.

4 A-weighted 98 dB CSchannel separation 100 dBPower dissipation (at fs= )Ppower dissipationaudio mode 18 mWvideo mode 24 mW2000 Jul 315 NXP SemiconductorsProduct specificationLow power audio DAC with PLLUDA1334 ATS6 BLOCK DIAGRAM handbook, full pagewidthMGL973 DACUDA1334 ATSNOISE SHAPERINTERPOLATION FILTERDE-EMPHASIS1415 DAC6 DIGITAL INTERFACEPLL16321451171312 VOUTRBCKVSSAWSVOUTLDATAIVDDAVDDD10 PLL0 Vref(DAC)VSSDSFOR0 SYSCLK/PLL18 MUTE9 Block Jul 316 NXP SemiconductorsProduct specificationLow power audio DAC with PLLUDA1334 ATS7 PINNINGNote1. Because of test issues these pads are not 5 V tolerant and both pads should be at power supply voltage level or at a maximum of V above that TYPEDESCRIPTIONBCK15 V tolerant digital input padbit clock inputWS25 V tolerant digital input padword select inputDATAI35 V tolerant digital input padserial data inputVDDD4digital supply paddigital supply voltageVSSD5digital ground paddigital groundSYSCLK/PLL165 V tolerant digital input padsystem clock input in video mode/PLL mode control 1 input in audio modeSFOR175 V tolerant digital input padserial format select 1 inputMUTE85 V tolerant digital input padmute control inputDEEM/CLKOUT95 V tolerant digital input/output padde-emphasis control input in audio mode/clock output in video modePLL0103-level input pad; note 1 PLL mode control 0 inputSFOR011digital input pad.

5 Note 1serial format select 0 inputVref(DAC)12analog padDAC reference voltageVDDA13analog supply padDAC analog supply voltageVOUTL14analog output padDAC output leftVSSA15analog ground padDAC analog groundVOUTR16analog output padDAC output righthandbook, halfpageUDA1334 ATSMGL97212345678161514131211109 VOUTRBCKVSSAWSVOUTLDATAIVDDAVDDDVref(DAC )VSSDSFOR0 SYSCLK/PLL1 PLL0 SFOR1 Pin Jul 317 NXP SemiconductorsProduct specificationLow power audio DAC with PLLUDA1334 ATS8 FUNCTIONAL clockThe UDA1334 ATS incorporates a PLL capable of generating the system clock. The UDA1334 ATS can operate in 2 modes: It operates as an asynchronous DAC, which means the device regenerates the internal clocks using a PLL from the incoming WS signal. This mode is called audio mode. It generates the internal clocks from a 27 MHz clock input, based on 32, 48 and 96 kHz sampling frequencies. This mode is called video video mode, the digital audio input is slave, which means that the system must generate the BCK and WS signals from the output clock available at pin CLKOUT of the UDA1334 ATS.

6 The digital audio signals should be frequency locked to the CLKOUT :1. The WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I/O data interface2. For LSB-justified formats it is important to have a WS signal with a duty factor of 50%. MODEA udio mode is enabled by setting pin PLL0 to LOW. De-emphasis can be activated via pin DEEM/CLKOUT according to Table audio mode, pin SYSCLK/PLL1 is used to set the sampling frequency range as given in Table 1 Sampling frequency range in audio MODEIn video mode, the master clock is a 27 MHz external clock (as is available in video environment). A clock-out signal is generated at pin DEEM/CLKOUT. The output frequency can be selected using pin PLL0. The output frequency is either MHz (256 48 kHz) with pin PLL0 being at MID level or MHz (384 48 kHz) with pin PLL0 being HIGH, as given in Table 2 Clock output selection in video modeNotes1. The supported sampling frequencies are: 96, 48 and 24 kHz or 64, 32 and 16 The supported sampling frequencies are: 96, 48 and 24 kHz; 72 and 36 kHz or 32 filterThe interpolation digital filter interpolates from 1fsto 64fs by cascading FIR filters (see Table 3).

7 Table 3 Interpolation filter shaperThe 5th-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC).SYSCLK/PLL1 SELECTIONLOWfs=16to50kHzHIGHfs= MHz clock; note MHz clock; note 2 LOWaudio modeITEMCONDITIONVALUE (dB)Pass-band ripple0fsto band> 50 Dynamic range0fsto >1142000 Jul 318 NXP SemiconductorsProduct specificationLow power audio DAC with stream DACThe FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. No post filter is needed due to the inherent filter function of the DAC.

8 On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output voltage of the FSDAC scales proportionally to the power supply resetThe UDA1334 ATS has an internal power -on reset circuit (see ) which resets the test control reset time (see ) is determined by an external capacitor which is connected between pin Vref(DAC) and ground. The reset time should be at least 1 s for Vref(DAC)< V. When VDDA is switched off, the device will be reset again for Vref(DAC)< the reset time the system clock should be , halfpageVDDAVref(DAC) V1312 MGT015 UDA1334 ATSC1 >10 FRESETCIRCUIT50 k 50 k power -on reset , (V) (V) (DAC)(V) >1 power -on reset Jul 319 NXP SemiconductorsProduct specificationLow power audio DAC with INTERFACE FORMAT SELECTThe digital audio interface formats (see ) can be selected via pins SFOR1 and SFOR0 as shown in Table the digital audio interface holds that the BCK frequency can be maximum 64 times WS WS signal must change at the negative edge of the BCK signal for all digital audio 4 Data format CONTROLThis function is only available in audio mode.

9 In that case, pin DEEM/CLKOUT can be used to activate the digital de-emphasis for kHz as given in Table 5De-emphasis control ( audio mode) CONTROLThe output signal can be soft muted by setting pin MUTE to HIGH as given in Table 6 Mute controlSFOR1 SFOR0 INPUT FORMATLOWLOWI2S-bus inputLOWHIGHLSB-justified 16 bits inputHIGHLOWLSB-justified 20 bits inputHIGHHIGHLSB-justified 24 bits inputDEEM/CLKOUTFUNCTIONLOWde-emphasis offHIGHde-emphasis onMUTEFUNCTIONLOW mute offHIGH mute on2000 Jul 3110 NXP SemiconductorsProduct specificationLow power audio DAC with PLLUDA1334 ATShandbook, full pagewidthMGS75216B5B6B7B8B9B10 LEFTLSB-JUSTIFIED FORMAT 24 BITSWSBCKDATARIGHT15181720192221232421B3 B4 MSBB2B23 LSB16B5B6B7B8B9B1015181720192221232421B3 B4 MSBB2B23 LSB16 MSBB2B3B4B5B6 LEFTLSB-JUSTIFIED FORMAT 20 BITSWSBCKDATARIGHT151817201921B19 LSB16 MSBB2B3B4B5B6151817201921B19 LSB16 MSBB2 LEFTLSB-JUSTIFIED FORMAT 16 BITSWSBCKDATARIGHT1521B15 LSB16 MSBB21521B15 LSBMSBMSBB221> = 812 3 LEFTI2S-BUS FORMATWSBCKDATARIGHT3> = Digital audio Jul 3111 NXP SemiconductorsProduct specificationLow power audio DAC with PLLUDA1334 ATS9 LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).

10 Notes1. All supply connections must be made to the same power ESD behaviour is tested according to JEDEC II Short-circuit test at Tamb=0 C and VDDA= 3 V. DAC operation after short-circuiting cannot be HANDLINGI nputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS THERMAL CHARACTERISTICS12 QUALITY SPECIFICATIONIn accordance with SNW-FQ-611-E .13 DC CHARACTERISTICSVDDD=VDDA= ; Tamb=25 C; RL=5k ; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise voltagenote 1 (max)maximum crystal temperature 150 CTstgstorage temperature 65+125 CTambambient temperature 40+85 CVeselectrostatic handling voltage human body model; note 2 2000+2 000 Vmachine model; note 2 250+250 VIsc(DAC)short-circuit current of DACnote 3output short-circuited to VSSA 450mAoutput short-circuited to VDDA 300mASYMBOLPARAMETERCONDITIONSVALUEUNITR th(j-a)thermal resistance from junction to ambientin free air145 analog supply voltagenote supply voltagenote analog supply currentaudio mode mAvideo mode mAIDDD digital supply currentaudio mode mAvideo mode mA2000 Jul 3112 NXP SemiconductorsProduct specificationLow power audio DAC with PLLUDA1334 ATSN otes1.