UltraScale Architecture System Monitor User Guide

1 UltraScale Architecture System MonitorUser GuideUG580 ( ) March 29, 2018 SYSMON User Guide2UG580 ( ) March 29, HistoryThe following table shows the revision history for this document. DateVersionRevision03/29 Differences from Previous Generations and Thermal Management. Revised Table 1-2 and Table 4-5. Revised description for VREFN in Table Figure 1-3. Revised the description for package pin VCC_PSADC in Table 1-2. Updated Temperature Sensor, including deleting Equations 1-2 through 1-5. Revised Table 3-13. Updated Automatic Channel Sequencer, ADC Channel Settling Time (4Eh, 4Fh), ADC Channel Averaging (47h, 4Ah, and 4Bh), and Thermal last paragraph in SYSMON Attributes.

2 Updated Temperature Sensor in Chapter 1. Added Figure 3-12 and Table 3-12. Added PMBus Examples. Revised Figure 1-2, Figure 2-5, Figure 2-6, Figure 3-1, Figure 3-2, Figure 3-7, Figure 3-17, and Figure 3-18. Added note for Table 3-13. Added important note for Table 3-14. Updated Table 1-1, Table 3-4, Table 3-5, Table 3-20, Table 4-1, Table 4-3, Table 4-8, Table 4-10, and Table 4-11. Updated Temperature Sensor in Chapter 2, including revising Equation 2-9 and Equation 2-10, and adding Equation 2-11 and Equation 2-12. Revised DRP I2C Interface. Deleted Table 3-18 SYSMONE1 I2C DRP Write Label Descriptions. Updated important notes in Continuous Sequence Mode (Slow Sequence - SYSMONE4).

3 Revised important note in Example Design Test dual sequence to slow sequence throughout. Updated Equation 1-3, Equation 2-9, Equation 2-10, Equation 4-1, Equation 4-2, and Equation 4-3. Updated Figure 3-2, Figure 3-7, Figure 4-1, and Figure 4-2. Updated Table 1-2, Table 1-3, Table 3-5, Table 4-2, Table 4-3, Table 4-5, and Table 4-6. Updated Default Mode, Continuous Sequence Mode (Slow Sequence - SYSMONE4), and Thermal Management. Standardized figure UltraScale +, Zynq UltraScale +, Virtex UltraScale +, and Kintex UltraScale + FPGA information throughout. Added SYSMONE1 and SYSMONE4 information last paragraph in SYSMON Overview. Updated Equation 1-2. Updated Temperature Sensor.

4 Updated first paragraph in Chapter 3, SYSMON Register Interface. Updated equations in Thermal Management. Revised second paragraph in Anti-Alias Filters. Updated values for Temp upper alarm trigger, OT upper alarm limit, Temp lower alarm reset, and OT lower alarm reset in Verilog instantiation in Example Design Instantiation. Updated Example Design Test Table 1-2 notes. Updated External Analog Inputs, Auxiliary Analog Inputs, I2C Slave Address Assignment, and Example Design Test Bench. Updated Temperature Sensor, page 28 to differentiate between using an external or on- chip reference. Updated Temperature Sensor, page 40 and Thermal Management, page 91. Updated Figure 2-6, Figure 4-3, and Figure first sentence in SYSMON Overview.

5 Updated placement of ferrite bead in Figure 1-3, Figure 3-19, and Figure 5-1. Added Equation 2-7, Equation 2-8, Equation 2-14, Equation 2-15, Equation 2-17, Equation 2-18, Equation 2-20, and Equation 2-21. Removed timing information from Figure 3-3. Updated SYSMON DRP JTAG Write Operation. Updated first paragraph in I2C Read/Write Transfers. Updated Supply Sensor Alarms and Thermal Management. Added information on TCL file in Example Design Instantiation. Clarified Note 2 in Table FeedbackSYSMON User Guide3UG580 ( ) March 29, SYSMON Overview, External Analog Inputs, Adjusting the Acquisition Settling Time, I2C Slave Address Assignment, External Multiplexer Operation, Reference Inputs (VREFP and VREFN), Anti-Alias Filters, and References.

6 Updated Figure 1-3, Figure 3-5, Figure 3-8, Figure 3-18, and Figure 5-3. Added calibration coefficients and notes to Figure 3-1. For ports I2C_SDA_IN and I2C_SCLK_IN, corrected port name by removing _IN. Updated Table 1-2, Table 1-4, Table 3-2, Table 3-5, and Table 3-9. Added IBUF_ANALOG. Removed references to AVCC, AVTT, and MGTVCCAUX. Added I2C Addr Meas and Reserved status registers to Table 3-1. Updated note in DRP JTAG Interface. Updated first paragraph in Chapter 4, SYSMON Operating Modes. Updated SYSMON Verilog example design in Example Design Xilinx FeedbackSYSMON User Guide4UG580 ( ) March 29, of ContentsRevision History .. 2 Chapter 1: Overview and Quick StartIntroduction to the UltraScale Architecture .

7 6 SYSMON Overview.. 7 SYSMON Pinout Requirements .. 12 Instantiating the SYSMON .. 18 Chapter 2: Basic FunctionalityADC Transfer Functions .. 29 Analog Inputs .. 32 Chapter 3: SYSMON Register InterfaceDynamic Reconfiguration Port (DRP) Timing .. 47 Status Registers .. 48 Control Registers .. 54 DRP Arbitration .. 59 DRP JTAG Interface .. 59 DRP I2C Interface .. 64 Chapter 4: SYSMON Operating ModesSingle Channel Mode .. 80 Automatic Channel Sequencer .. 80 Sequencer Modes .. 86 External Multiplexer Mode .. 88 Automatic Alarms .. 90 Chapter 5: Application GuidelinesReference Inputs (VREFP and VREFN) .. 95 Analog Power Supply and Ground.

8 96 External Analog Inputs .. 99 SYSMON Software Support .. 100 Send FeedbackSYSMON User Guide5UG580 ( ) March 29, A: Additional Resources and Legal NoticesXilinx Resources .. 111 Solution Centers .. 111 Documentation Navigator and Design Hubs .. 111 References .. 112 Please Read: Important Legal Notices .. 113 Send FeedbackSYSMON User Guide6UG580 ( ) March 29, 1 Overview and Quick StartIntroduction to the UltraScale ArchitectureThe Xilinx UltraScale Architecture is the first ASIC-class All Programmable Architecture to enable multi-hundred gigabit-per-second levels of System performance with smart processing, while efficiently routing and processing data on- chip .

9 UltraScale Architecture -based devices address a vast spectrum of high-bandwidth, high-utilization System requirements by using industry-leading technical innovations, including next-generation routing, ASIC-like clocking, 3D-on-3D ICs, multiprocessor SoC (MPSoC) technologies, and new power reduction features. The devices share many building blocks, providing scalability across process nodes and product families to leverage System -level investment across platforms. Virtex UltraScale + devices provide the highest performance and integration capabilities in a FinFET node, including both the highest serial I/O and signal processing bandwidth, as well as the highest on- chip memory density.

10 As the industry's most capable FPGA family, the Virtex UltraScale + devices are ideal for applications including 1+Tb/s networking and data center and fully integrated radar/early-warning UltraScale devices provide the greatest performance and integration at 20 nm, including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA at the 20 nm process node, this family is ideal for applications including 400G networking, large scale ASIC prototyping, and UltraScale + devices provide the best price/performance/watt balance in a FinFET node, delivering the most cost-effective solution for high-end capabilities, including transceiver and memory interface line rates as well as 100G connectivity cores.