Understanding Voltage Variations in Chip Multiprocessors ...

1 Understanding Voltage Variations in chip Multiprocessors using a distributed power -Delivery Network Meeta S. Gupta , Jarod L. Oatley , Russ Joseph , Gu-Yeon Wei and David M. Brooks . Division of Engineering and Applied Sciences, Harvard University, Cambridge, MA. {meeta, jloatley, wei, Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL. Abstract Recent efforts to address microprocessor power to localized supply fluctuations due to package connections dissipation through aggressive supply Voltage scaling and power and the on- chip power -supply grid.}

2 In this paper, we describe management require that designers be increasingly cognizant of an architecture-level, fine-grained, power -delivery model that power supply Variations . These Variations , primarily due to fast changes in supply current, can be attributed to architectural captures localized Voltage Variations across the entire chip . gating events that reduce power dissipation. In order to study Current technology trends are moving towards chip multi- this problem, we propose a fine-grain, parameterizable model processor (CMP) architectures like IBM's Cell processor [3].

3 For power -delivery networks that allows system designers to and Intel's Core Duo processor [4]. It is important to un- study localized, on- chip supply fluctuations in high-performance derstand inter-core Voltage Variations for multiple cores on microprocessors. Using this model, we analyze Voltage Variations in the context of next-generation chip -multiprocessor (CMP) a CMP machine. Core utilization patterns and activity in- architectures using both real applications and synthetic current teractions between cores can lead to large inter-core Voltage traces. We find that the activity of distinct cores in CMPs present Variations .

4 In order to understand these inter-core Variations , several new design challenges when considering power supply a fine-grained power -delivery network is needed to model noise, and we describe potentially problematic activity sequences these effects. Using a distributed power -delivery model of the that are unique to CMP architectures. on- chip power -supply grid, we explore the repercussions of different combinations of activity patterns. I. I NTRODUCTION. The main contributions of our work are: Supply- Voltage fluctuations have emerged as a serious cause 1) We provide a parameterizable, distributed , power - for concern in high-performance processor design.

5 These per- delivery model, which can be configured to closely turbations occur when the processor demands rapidly change match measured impedances found in the literature [5]. current consumption over a relatively small time scale. Since 2) This paper investigates Voltage Variations across a CMP. the power -delivery subsystem can have substantial parasitic machine using both real and synthetic activity patterns. inductance, this current variation produces Voltage ripple on 3) We illustrate possible problematic activity sequences the chip 's supply lines. This is significant because if the that are unique to CMP architectures.

6 Supply Voltage rises or drops below a specific tolerance range, The paper is organized as follows: Section II describes the CPU may malfunction. This fundamental challenge is the modeling of a distributed power -delivery network. The known as the dI/dt problem since the magnitude of these different types of activities and their effects on Voltage vari- Voltage ripples is affected by the instantaneous change of ations are studied in Section III. Section IV reviews prior current with respect to time. Current fluctuations are primarily research generally related to power delivery modeling.

7 Finally, derived from dynamic resource utilization fluctuations, which Section V concludes the paper. are heavily influenced by architectural power -saving events such as clock- and power -supply gating and idle/sleep modes. II. M ODELING THE P OWER D ELIVERY N ETWORK. Thus, analysis at the architecture-level is critical to allow de- This section presents a detailed yet flexible power -delivery signers to understand the impact of these techniques on power - model that captures the characteristic mid-frequency reso- supply Voltage stability under a variety of power -delivery and nance, transients related to board and package interfaces, and package-modeling assumptions.

8 Localized on- chip Voltage Variations . Previous architecture-level dI/dt studies ([1] and [2]) have Figure 1(a) presents our detailed model of the power - used lumped models of the on- chip power -delivery network delivery network with a distributed on- chip power -supply to capture the mid-frequency resonance. The major limitation grid. The off- chip network includes the motherboard, package, of these architectural models is the global treatment of on- and off- chip decoupling capacitors and parasitic inductances, chip VDD/GND as single nodes, which fails to capture local modeled via a ladder RLC network.

9 Figure 1(b) illustrates on-die Voltage Variations across the chip . As the effects of the distributed on- chip grid model used in our analysis. The supply variation play a more prominent role in performance C4 bumps are modeled as parallel connections (via RL pairs). and reliability, architects will have to pay closer attention that connect the grid to the off- chip network, with each grid (a) Package model (b) On-die grid model Fig. 1. power delivery model Off chip Impedance Plot 7 with respect to the available Pentium 4 measurements [5]. The slight difference in the on- chip impedance, shown in 6.

10 Figure 2(b), can be attributed to the slightly higher bump 5 resistances in the lumped model, which are required to match Impedance (mOhm). 4. off- chip impedances. It is important to note these parameters Lumped Model distributed Model can easily be modified to model different architectures and 3. power -delivery networks. 2. Resistance Value Inductance Value Capacitance Value 1. Rpcb,s mohm Lpcb 21 picoH Cpcb 240 F. 0 5 Rpcb,p mohm 6 7 8 9. 10 10 10 10 10. Frequency (Hz) Rpkg,s 1 mohm Lpkg 120 picoH Cpkg 26 F. Rpkg,p mohm Lpkg,p picoH. (a) Off- chip Rbump,lumped mohm Lbump,lumped pH.