Verilog HDL Syntax - chorogyi.tistory.com

1 Verilog HDL Syntax SoC . HDL ? HDL(Hardware Description Language). VLSI time-to-market . GLM schematic . HDL .. Structural Functional B.. A. concurrent language C. -2- SoC . HDL . vhdl . ADA Syntax 1987 (IEEE 1076).. Verilog HDL. C Syntax Gateway Design System Cadence . 70% . -3- SoC . HDL .. -4- SoC . ASIC . Design Specification Behavioral Description RTL Description (HDL). Functional Verification Logic Synthesis Gate-Level Netlist Logical Verification Floor Planning Back annotation Automatic Place & Route Physical Layout Layout Verification Implementation -5- SoC . Verilog . Verilog .. 3 . Structural model primitive (built-in Verilog logic gate, , ) . Dataflow model expression combinational logic . assign target = expression . Arithmetic operators: +, -, *, /, %, >>, <<. Relational operators: <, <=, ==, !=, >=, >, ===, !==. Logical operators: &&, ||, !

2 , ?: Bit-wise operators: ~, &, |, ^, ~^, ^~. Reduction operators: &, ~&, |, ~|, ^, ~^. Concatenation, replication: {sigs } {number{ }}. -6- SoC . Verilog . Behavioral model Blocking assignment, non-blocking assignment, conditional statement, case statement always, initial block .. RTL . Register Transfer Level . register .. Clock .. dataflow model + behavioral model . -7- SoC . Verilog . (Module). Verilog HDL .. Statement terminator semicolon . Timing specification . module module_name(port_list);. port declarations data type declarations circuit functionality timing specifications endmodule -8- SoC .. module module Timing TimingSpecificatons Specificatons (port (portlist). list). port port data datatype type circuit circuit subprograms subprograms declarations declarations declaratoins declaratoins functionality functionality instantiation instantiation input input net net task task continuous continuous procedural procedural output output register register function function assignment assignment blocks blocks input parameter system input parameter assign initial systemtasks tasks assign initialblock block compiler compiler always alwaysblock block directives directives -9- SoC.

3 Module Add_half_1 (sum, c_out, a, b); . input a, b; . output sum, c_out;. wire c_out_bar; . xor (sum, a, b);. function . nand (c_out_bar, a, b); Predefined primitives . not (c_out, c_out_bar); instantiation endmodule a sum b Add_half_1 c_out c_out Sum = a ^ b C_out = a & b -10- SoC .. module Add_half_2 (sum, c_out, a, b);. input a, b;. output sum, c_out;. assign {c_out, sum} = a + b; function . endmodule continuous assignment .. a sum b Add_half_2 c_out Sum = a ^ b C_out = a & b -11- SoC .. module Add_full (sum, c_out, a, b, c_in);. input a, b, c_in;. output sum, c_out;. half_adder . wire w1, w2, w3;. Structural description module instantiation . Add_half_1 M1 (w1, w2, a, b); (parent module / child module). Add_half_2 M2 (sum, w3, w1, c_in); module instantiation . or (c_out, w2, w3); module instance name . endmodule (primitive instantiation optional).

4 C_in sum M2. w1 w3. a M1 w2 c_out b -12- SoC .. module full_adder (sum, carryout, in1, in2, carryin); sumHA = a ^ b c_outHA = ab sumFA = (a + b) ^ c_in input in1, in2, carryin;. c_outFA = (a + b) c_in + abc_in output sum, carryout;. Half_adder . sum +, reg sum, carryout; c_out & .. always @(in1 or in2) begin {carryout, sum} = in1+in2+carryin; sumFA = (a + b) + c_in end c_outFA = a&b | a&b&c_in endmodule in1 in2. carryout full_adder carryin sum -13- SoC .. module stimulus;. reg clk;. reg reset;. wire [3:0] q;. ripple_carry_counter r1(q, clk, reset);. initial clk = 1'b0;. always #5 clk = ~clk;. initial begin reset = 1'b1; task Timing #15 reset = 1'b0; specification #180 reset = 1'b1;. #10 reset = 1'b0;. #20 $finish;. end initial $ monitor($time, output q = %d , q);. endmodule -14- SoC .. list : module mux_latch(y_out, sel_a, sel_b, data_a, data_b).

5 Input : . output : . inout : .. <port type> <port_name>;.. input sel_a, sel_b, data_a, data_b;. output y_out;. input [3:0] a;. output [3:0] a, b;. -15- SoC .. 0 0 False 1 1 True X Unknown . Z High impedance . Integer, real, time .. integer Count 32 bit integer integer K[1:63] Array of 64 integers -16- SoC .. ( ).. reg : register (latch flip-flop).. always, initial . : reg alu_reg;. reg [7:0] alu_reg;. wire : net ( ).. assign . : wire adder_out;. wire [15:0] adder_out, mult_out;. constant . -17- SoC .. Sized unsized . Sized . : <size>'<base format> <number>. : 3'b010 //3 prefix size . Unsized . Base format default decimal . Size default 32-bit . : 321 //32-bit decimal number 321 . Base format Decimal : d D. Hexadecimal : h H. Binary : b B. Octal : o O. -18- SoC .. <size> . : -8'd3 //3 2 8bit . : 4'd-2.. MSB 0, X, Z . MSB 0, X, Z . : 3'b01 = 3'b001, 3'bx1 = 3'bxx1 , 3'bz = 3'bzzz MSB 1.

6 MSB 0 . : 3'b1 = 3'b001. -19- SoC .. Number #Bits Base Dec. Equiv. Stored 10 32 Decimal 10 2'b10 2 Binary 2 10. 3'd5 3 Decimal 5 101. 8'o5 8 Octal 5 00000101. 8'ha 8 Hex 10 00001010. 3'b01x 3 Binary - 01x 12'hx 12 Hex - xxxxxxxxxxxx 8'b0000_0001 8 Binary 1 00000001. 8'bx01 8 Binary - xxxxxx01. 8'HAD 8 Hex 173 10101101. -20- SoC .. Binary . Operator Name Comments + Addition - Subtraction * Multiplication / Division Divide by zero produces an x. % Modulus ( ) ( ). A = 4'b0011, B = 4'b0100, D = 6, E =4 operand bit x . A * B = 4'b1100 x . D / E = 1 //Truncates any fractional part in1 = 4'b101x, in2 = 4'b1010 . A + B = 4'b0111 Sum = in1 + in 2; //sum 4'bx B A = 4'b0001 -7 % 2 = -1 // operand . 13 % 3 = 1 7 % -2 = 1 // operand . -21- SoC .. Operator Name Comments > Greater than >= Greater than or equal < Less than <= Less than or equal == Logical equality !

7 = Logical inequality ( ). ain = 3'b010, bin = 3'b100, cin = 3'b111, din = 3'b01z, ein = 3'b01x . ain > bin false(1'b0) . ain < bin ture(1'b1) . ain >= bin unknown(1'bx) . ain <= ein unknown(1'bx) . -22- SoC .. Operator Name Comments ! Logical negation && Logical AND. || Logical OR. ( ). A = 3 ; B = 0;. A && B //Evaluates to 0. Equivalent to (logical 1 && logical 0). A || B //Evaluates to 1. Equivalent to (logical 1 && logical 0). !A //Evaluates to 0. Equivalent to not(logical 1). !B //Evaluates to 1. Equivalent to not(logical 0). A = 2'b0x ; B = 2'b10;. A && B //Evaluates to x. Equivalent to (x && logical 1). (a == 2) && (b == 3) //Evaluates to 1 if both a == 2 and b==3 are true -23- SoC .. Bitwise . Operator Name Comments ~ Bitwise negation & Bitwise AND. | Bitwise OR. ^ Bitwise XOR. ~& Bitwise NAND. ~| Bitwise NOR. ~^ or ^~ Bitwise XNOR Bitwise NOT XOR.

8 Operand operand 0 left-extend ( ). X = 4'b1010, Y = 4'b1101, Z = 4'b10x1 . ~X //Result is 4'b0101. X & Y //Result is 4'b1000. X|Y //Result is 4'b1111. X^Y //Result is 4'b0111. X ^~ Y //Result is 4'b1000. X & Z //Result is 4'b10x0. -24- SoC .. Unary Reduction . Operator Name Comments & AND reduction | OR reduction ^ XOR reduction ~& NAND reduction ~| NOR reduction ~^ XNOR reduction vector bit . X Z . unknown known . ( ). ain = 5'b10101, bin = 4'b0011, cin = 3'bz00, din = 3'bx011 . &ain //Result is 1'b0. ~&ain //Result is 1'b1. |cin //Result is 1'bx &din //Result is 1'b0. -25- SoC .. Equality . Operator Name Possible Logic Comments Value == Equality 0, 1, x != Inequality 0, 1, x === Case equality 0, 1 including x and Z. !== Case inequality 0, 1 including x and Z. case equality case inequality operand X Z unknown ( ). A = 4, B = 3, X = 4'b1010, Y = 4'b1101, Z = 4'b1xxz, M = 4'b1xxz, N = 4'b1xxx.

9 A == B //Result is logical 0. X != Y //Result is logical 1. X == Z //Result is x Z == M //Result is logical 1(all bits match, including x and z). Z == N //Result is logical 0(least significant bit does not match). M != N //Result is logical 1. -26- SoC .. Operator Name Comments << Shift left Vacated bit positions are filled with zeros, e. g., A = A << 2; shifts A two bits to left with zero fill. >> Shift right Vacated bit positions are filled with zeros. ? : Conditional Assigns one of two values depending on the conditional expression. E. g., A = C>D ? B+3 : B-2 means if C greater than D, the value of A is B+3 otherwise B-2. { } Concatenate ain = 3'b010, bin = 4'b1100. {ain, bin} results 7'b0101100. {{}} Replicate {3{2'b10}} results 6'b101010. -27- SoC . Multi bit . [MSB:LSB]. Input [7:0] abus; reg [15:8] add;.. assign abc = abus[5] ; assign abus[5] = abc.

10 Assign abcd[15:0] = {abus[7:0],add[15:8]} ;. -28- SoC . Array Register array . Reg [15:0] mem [0:255];. mem 16bit * 256word, 512 byte . resister bit . word . Bit . net . Ex) wire [15:0] temp;. assign temp = mem [100];. -29- SoC . (Description). (Structural description). Explicit structural description Primitive instance . Implicit structural description Continuous assignment . (Behavioral description).. initial, always behavior . Procedural block procedural statement . -30- SoC .. Explicit description module 8bit_or_gate (y, a, b) ; module 8bit_or_gate (y, a, b) ;. input [7:0] a, b ; input [7:0] a, b ;. output y ; output y ;. or G1 (y, a, b) ; or8bit (y, a, b) ;. endmodule endmodule Primitive . Implicit description module 8bit_or_gate (y, a, b) ;. input [7:0] a, b ;. output y ;. assign y = a | b ;. endmodule -31- SoC . Primitives Predetermined primitives Combinationa Three MOS CMOS Bi-Directional Pull l logic State Gates Gates Gates Gates and bufif0 nmos cmos tran pullup nand bufif1 pmos rcmos tranif0 pulldown or notif0 rnmos tranif1.