VESA DisplayPort Standard - GitHub Pages

1 VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Copyright 2007-2010 Video Electronics standards Association Page 1 of 515 DisplayPort Standard 860 Hillview Court, Suite 150 Phone: 408 957 9270 Milpitas, CA 95035 Fax: 408 957 9277 URL: VESA DisplayPort Standard Version 1, Revision 2 January 5, 2010 Purpose The purpose of this document is to define a flexible system and apparatus capable of transporting video, audio and other data between a Source Device and a Sink Device over a digital communications interface. Summary The DisplayPort Standard specifies an open digital communications interface for use in both internal connections, such as interfaces within a PC or monitor, and external display connections.

2 Suitable external display connections include interfaces between a PC and monitor or projector, between a PC and TV, or between a device such as a DVD player and TV display. DisplayPort is revised to correct errata items in and add clarifications to DisplayPort Standard Version 1, Revision 1. DisplayPort Ver. is revised to add enhancements including higher speed operation, more flexible topology management, multiple streams on a single connection, higher speed Auxiliary Channel communications, improved support for audio, and a new smaller connector. It also corrects errata items in and adds clarifications to DisplayPort Standard Version 1, Revision 1a. VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Copyright 2007-2010 Video Electronics standards Association Page 2 of 515 Table of Contents Preface ..15 Revision History ..20 1 Introduction.

3 21 DisplayPort Standard Organization ..21 DisplayPort Objectives ..21 Key Industry Needs for DisplayPort ..22 DisplayPort Technical DisplayPort External Connection DisplayPort Internal Connection DisplayPort CE Connection Objectives ..24 Content Protection for DisplayPort ..24 Acronyms ..24 Glossary ..27 Reference Documents ..31 Nomenclature for Bit and Byte Bit Ordering ..32 Byte Ordering ..33 Overview of DisplayPort ..34 Make-up of the Main Link ..34 Make-up of AUX Link Configuration and Management ..35 Layered, Modular Architecture ..36 2 Link Layer ..37 SST Mode Number of Lanes and Per-lane Data Rate (Applicable both in SST and MST Modes) ..38 Number of Main, Uncompressed Video Streams in SST Mode ..38 Basic Functions (Applicable both in SST and MST Modes) ..38 DisplayPort Device Types and Link Topology in SST Isochronous Transport Services in SST Main Stream to Main Link Lane Mapping in the Source Device.

4 43 Stream Reconstruction in the Sink ..71 Stream Clock Recovery ..72 Main Stream Attribute Data Transport ..74 Secondary-data Packing Formats ..79 ECC for Secondary-data AUX CH States and Arbitration ..107 AUX CH STATES Overview ..107 Link Layer Arbitration Policy Maker AUX CH Management ..111 Detailed uPacket TX AUX CH State Description ..112 Detailed uPacket RX AUX CH State Description ..113 Overview of DP Multi-Stream Transport (MST) Isochronous Transport Connection-oriented Transport ..115 Layers of DP Isochronous Transport Service ..117 Sideband CH Communications ..121 Topology Management Layer ..122 Primitives of MST DP Devices and Device Types ..122 MST Topologies ..125 MST Device Topology Manager and Topology Assistant ..127 VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Copyright 2007-2010 Video Electronics standards Association Page 3 of 515 Topology Topology Maintenance.

5 128 Topologies with SST-only Source devices ..129 Loop Handling ..129 Multi-Stream Transport Link Timing Generation Based on Multi-Stream Transport Packet ..135 Symbol Sequence Mapping into VC Payload ..136 Time Slot Count Allocation to VC VC Payload Allocation Synchronization ALLOCATE_PAYLOAD Timing Impacts of Various Events on VC Payload ID Robustness Control Functions, Control Symbols and K-Code Assignment ..164 Conversion Between MST and SST Symbol MTPH Usages for CP Extension in MST Mode ..167 AUX Transaction Syntax in Manchester Transaction Format ..170 Command definition ..171 AUX Transaction Response/Reply Time-outs ..173 Native AUX Request Transaction Native AUX Reply Transaction Syntax ..174 I2C Bus Transaction Mapping onto AUX Syntax ..174 Conversion of I2C Transaction to Native AUX Transaction (Informative) ..192 I2C-overAUX Transaction Clarifications and Implementation Rules.

6 192 Transaction Syntax in FAUX Transaction Format ..202 AUX CH Stream Transport Initiation Sequence ..203 Stream Transport Termination AUX Link AUX Device Services ..253 Protocol Differentiation for Embedded DisplayPort (eDP) ..255 Overview ..255 Protocol Differentiation eDP Source Behavior (Informative)..255 Symbol Error Rate Measurement Pattern Output (Informative) ..256 Messaging AUX Client ..258 Messaging AUX Client Layers ..259 Message Transaction Sideband MSG Layer ..268 AUX CH Support for Messaging AUX RAD (Relative Address) Updated by MST Devices in the Path ..274 Broadcast Message Transactions ..275 Message Error Handling ..279 Descriptions of Available Message Transaction Audio-to-Video & Audio-to-Audio Synchronization ..297 Overview ..297 DisplayPort AV Sync Data Block (AVSDB) ..298 Delay Compensation ..298 Global Time Code and Audio Inter-channel Sync.

7 304 Global Time Code ..304 Application of GTC for Audio Inter-channel Synchronization ..307 3 Physical Layer ..309 PHY Link Layer-PHY Interface PHY-Media Interface Signals ..311 VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Copyright 2007-2010 Video Electronics standards Association Page 4 of 515 Compliance Measurement Electrical Signal Definitions ..319 Scrambling ..323 Symbol Coding and Serialization/De-serialization ..324 DP_PWR for Box-to-Box DisplayPort DP_PWR User Detection Method ..326 DP_PWR Inrush Voltage Over-Current Hot Plug/Unplug Detect Circuitry ..327 AUX AUX Channel Logical Sub-block ..329 AUX Channel Electrical Sub-block ..341 Main Main Link Logic Sub-block ..353 Main Link Electrical Sub-Block ..362 Transmitter and Receiver Electrical Parameters.

8 362 ESD and EOS Protection ..378 4 Mechanical ..379 Cable-Connector Assembly Specifications (for box-to-box)..379 Cable-Connector Assembly Definition ..380 Type of Bulk Cable ..383 Impedance Profile ..384 Insertion Loss & Return Loss ..386 High Bit Rate Cable-Connector Assembly Specification ..387 Reduced Bit Rate Cable-Connector Assembly Specification ..397 Connector Specification ..401 External full-size connector ..401 Mini DisplayPort External Panel-side Internal Connector (Informative)..438 5 Source/Sink/Branch Device Policy Requirements for Interoperability ..446 Source Device in SST Mode ..446 Stream Source Source Device Link Configuration Requirement ..449 Source Device Behavior on Stream Timing Source Device Behavior upon HPD Pulse Downstream Device uPacket RX Power Management by a Source Device ..452 Source Device Connected to a Branch Sink Device in SST Stream Sink Requirement.

9 452 Sink Device Link Configuration Sink Device Behavior on Stream Timing Change ..454 Toggling of HPD Signal for Status Change Sink Device uPacket RX Power- save Mode ..454 Branch Device in SST-only Mode ..458 EDID Access Handling Requirement ..458 Branch Device Link Configuration Requirements ..458 Source Device in MST Sink Device in MST Mode ..463 Branch Device in MST Mode ..463 Cable-Connector Assembly ..463 Box-to-Box, End-User-Detachable Cable Assembly ..463 Embedded and Captive Cable Assembly ..464 VESA DisplayPort Standard MEMBER USE ONLY. DISTRIBUTION TO NON-MEMBERS IS PROHIBITED. Copyright 2007-2010 Video Electronics standards Association Page 5 of 515 6 Appendix A: Audio Transport (Informative)..465 Audio Stream Components ..465 Association of Three Packet Types via Packet ID ..465 Scheduling of Audio Stream Packet Transmission.

10 465 Handling of an Audio Format Change ..466 Structure of Audio Stream One or Two Channel Audio ..467 Three to Eight Channel Audio ..467 Channel-to-Speaker Mapping ..468 Transfer of Sample Frequency Information ..469 7 Appendix B: Sink Event Notification Example (Informative) ..470 Mutual Identification by Source and Sink ..470 IRQ_HPD Pulse and Sink-Specific 8 Appendix C: Link Quality Management (Informative) ..471 Marginal Link Quality ..471 Tolerance to Bit Link Long-term Link Quality Monitoring (Guidelines) ..472 9 Appendix D: Electrical Specifications (Informative) ..473 AUX Parameters ..473 FAUX Electrical Parameter Background ..474 Main Link Parameters ..477 The Dual-Dirac Jitter Model ..481 10 Appendix E: Scrambler C Code Reference (Informative) ..483 11 Appendix F: Topology Management/Payload Bandwidth Management Usage Examples ..488 12 Appendix G: Link Management During System Initialization (Informative).