VHDL Reference Manual

1 VHDL ReferenceManual096-0400-003 March 1997 Synario Design Automation, a division of Data I/O, has made every attempt toensure that the information in this document is accurate and complete. SynarioDesign Automation assumes no liability for errors, or for any incidental,consequential, indirect or special damages, including, without limitation, loss of use,loss or alteration of data, delays, or lost profits or savings, arising from the use ofthis document or the product which it part of this document may be reproduced or transmitted in any form or by anymeans, electronic or mechanical, for any purpose without written permission fromData Design Automation10525 Willows Road , Box 97046 Redmond, Washington 98073-9746 USAC orporate Switchboard: (206) 881-6444 Sales: 1-888-SYNARIO or Support: 1-800-789-6507 or Wide Web.

2 Synario , Synario ECS , ABEL , and Synario Design Automation are eithertrademarks or registered trademarks of Data I/O Corporation in the United Statesand/or other countries. Other trademarks are the property of their respectiveowners. Copyright 1993-1997 Synario Design Automation , a division of DataI/O Corporation. All rights 1993-1997 Synario Design Automation, a division of Data rights copyright:Microsoft Corporation. All rights reserved;Model Technology. All rights reserved;VHDL Reference ManualiiiTable of Contents1. Language of a VHDL Design and Sequential Std_ulogic and Std_logic Data Defined Types and and Logic How to Write Synthesizable of ContentsivVHDL Reference ManualDescribing Combinational and Conditional Statement: Conditional Signal Statement.

3 Selected Signal Replicated and Sequential Clocks and Clock Finite State State of State Unwanted How to Control the Implementation of Enumerated Review of Enumerated of Enumerated One hot t-cares and Enumerated Output Std_logic to Describe Output Output Feedback of ContentsVHDL Reference ManualvSelecting a Base Data the Integer Bit and Bit_vector Std_ulogic and Std_ulogic_vector Std_logic and Std_logic_vector IEEE Unsigned/Signed of Don't Device Fitting VHDL Datapath Inferencing Datapath of Inferencing of How to Infer Datapath How to Manage VHDL Design Large And Visibility Packages For Common Design Search Work Dataio and Generics Schematics With A Top-Level Schematic With Lower-Level Schematics With Generic Symbols With VHDL Quick of ContentsviVHDL Reference ManualReserved Syntax and Unsupported VHDL for the ABEL-HDL Design I/O in Design I/O in and Node Pin Numbers in Pin and Node Numbers in Combinational Logic in Combinational Logic in Registers in Registers in Unwanted State Machines in State Machines in Standard ABEL-HDL Design in ABEL-HDL Language Reference Manual1-11.

4 IntroductionThis Manual discusses VHDL and the Synario Programmable ICSolution. This Manual is intended to supplement the materialpresented in the Programmable IC Entry following topics are discussed in this Manual : VHDL Language Structure How to write Synthesizable VHDL How to control the implementation of a VHDL Design VHDL Datapath Synthesis How to Manage VHDL Design Hierarchies VHDL Quick Reference Limitations ( constraints and unsupported Constructs) VHDL for ABEL-HDL users ABEL-HDL Language Reference (Dot extensions)Introduction1-2 VHDL Reference ManualVHDL Reference Manual2-12. Language StructureVHDL is a hardware description language (HDL) that contains thefeatures of conventional programming languages such as Pascal or C,logic description languages such as ABEL-HDL, and netlist languagessuch as EDIF.

5 VHDL also includes design management features, andfeatures that allow precise modeling of events that occur over chapter introduces a subset of the VHDL language that allows youto begin creating synthesizable designs, and is not intended todescribe the full language. For further information on VHDL, consult astandard VHDL Reference book. A number of these books are listed atthe end of this VHDL Synthesizer supports most of the VHDL language, asdescribed in IEEE Standard 1076-1993. The meaning of some sectionsof the language, however, is unclear in the context of logic of this are found in the standard package textio. The file I/Ooperations supported by textio are useful for simulation purposes butare not currently synthesizable. For sample syntax and a list of VHDL statements supported by theVHDL Synthesizer, see appendix A, Quick Reference .

6 For a list of exceptions and constraints on the VHDL Synthesizer'ssupport of VHDL, see appendix B, Limitations. This chapter shows you the structure of a VHDL design, and thendescribes the primary building blocks of VHDL used to describe typicalcircuits for synthesis: Library (Design) Units Statements Objects Types Operators AttributesIn addition, the three primary methods of VHDL design are discussed: Dataflow VHDL Behavioral VHDL Structural VHDLL anguage Structure2-2 VHDL Reference ManualStructure of a VHDL Design DescriptionThe basic organization of a VHDL design description is shown in Figure2-1. The sample file shown includes an entity-architecture pair and 2-1: The Structure of a VHDL Design Description----------------------------- ------------- PREP Benchmark Circuit #1: Data Path---- Copyright 1993, Data I/O Copyright 1993, Metamor, typedef is subtype byte is bit_vector (7 downto 0);end;use ;entity data_path is port (clk,rst,s_1 : in boolean; s0, s1 : in bit; d0, d1, d2, d3 : in byte; q : out byte);end data_path;architecture behavior of data_path is signal reg,shft : byte; signal sel: bit_vector(1 downto 0);begin process (clk,rst) begin if rst then -- async reset reg <= x"00"; shft <= x"00".

7 Elsif clk and clk'event then -- define a clock sel <= s0 case sel is -- mux function when b"00" => reg <= d0; when b"10" => reg <= d1; when b"01" => reg <= d2; when b"11" => reg <= d3; end case; if s_1 then -- conditional shift shft <= shft(6 downto 0) & shft (7); else shft <= reg; end if; end if; end process; q <= shft;end behavior;CommentsPackageUse ClauseEntitySequentialStatementsProcessS tatementsArchitectureLanguage StructureVHDL Reference Manual2-3 Library UnitsLibrary units (also known as design units) are the main components ofa VHDL description. They consist of the following kinds of declarations: Package (optional) Entity Architecture Configuration (optional)A design may include any number of package, entity, architecture, andconfiguration declarations.

8 The relationship of the four types of designunits is illustrated in Figure 2-2. Note that only the entity andarchitecture design units are required; the package and configurationdesign units are 2-2: Relationship of VHDL design unitsPackageA package is an optional library unit used for making shareddefinitions. An example of something that might be shared is a typedefinition, as shown in Figure 2-1. When you make definitions in apackage, you must use the library and use statements to make thepackage available to other parts of the VHDL example_arithmetic is type small_int is range 0 to 7;end example_arithmetic;Language Structure2-4 VHDL Reference ManualEntityEntities contain the input and output definitions of the design. In VHDL designs that contain a hierarchy of lower-level circuits, the entityfunctions very much like a block symbol on a schematic.

9 An entityusually has one or more ports, which are analogous to the pins on aschematic symbol. All information must flow into and out of the entitythrough the ports, as shown:library my_lib;use ;entity ent is port (a0,a1,b0,b1 : in small_int; c0,c1 : out small_int);end ent;Note that this example references the package defined in the previoussection to gain access to the type small_int. Each port has a modethat defines a direction: in, out, inout, or in, out, and inout all have the obvious meanings. Portsdeclared to be of type out may not be read. Therefore, theassignment:c1 <= c0;would be illegal since c0 is declared to be an out port. Mode buffer isequivalent to mode out except that the value of the port may be readwithin the addition to ports, entities may also contain generics. Generics aresimilar to ports, except that they pass static information.

10 You can usegenerics to create two or more instances of an entity where theinstances behave in different ways. A common use of generics is ingate-level modeling, where generics pass delay values into the model,as shown:library my_lib;use ;entity ent is generic (t_rise, t_fall : time := 5 ns); port (a0,a1,b0,b1 : in small_int; c0,c1 : out small_int);end ent;The preceding example specifies a rise and fall delay using the pre-defined type time, and gives the delays a default value of 5 ns. Notethat if you use generics when writing code for synthesis, all genericparameters must be given default StructureVHDL Reference Manual2-5 ArchitectureThe architecture is the actual description of the design. If you thinkof an entity as a functional block symbol on a schematic, then anarchitecture describes what's inside the block.