VME Data Acquisition System - Tata Institute of ...

1 VME data Acquisition System : Fundamentals and BeyondAbhinav KumarBhabha Atomic Research Centre, MumbaiMarch 2011 Chapter 1--------------------------------Introdu ction to VME Chapter 2--------------------------------VME Architecture Chapter 3-------------------------------- data Acquisition Setup under VMEC hapter 4-------------------------------- data Acquisition with VME Modules using LAMPSP resentation Outline Introduction to VME VME stands for VERSA Module Euro cardintroduced in 1981 for industrial, commercial and military applications. Electrical and mechanical specifications are defined by the standard.

2 VME bus is a master slave computer architecture. The signaling scheme is asynchronous, meaning that the transfer is not tied to the timing of a bus clock. VITA(VME International Trade Association) is the organisation whose purpose is to promote and develop the VME Unlike NIM and CAMAC, the VME was created for the industry and not for physics applications However, the North American, European and Japanese physics communities have joined to work with the VITA and found the VME International Physics Association (VIPA) Two standards have been created.

3 VME/V430 (1990) and VME64xP (1998)Extension of VME for Physics ApplicationVME Cratesmart fan unitsVME masterVME slavepower supplybackplaneVME ComponentsOptical LinkVME Modules supported by LAMPSS ingle Width 6 U Module having 32 Peak Sensing Analog to Digital conversion channel density12 bit >s / 32 channel conversion timeZero and overflow suppression for each channel32 event buffer memoryV785 ADCV830 ScalerSingle Width 6 U Module32 Channel Latching ScalerThe counters values can be read on the fly from VME without interfering on data Acquisition these, as of date.

4 LAMPS provides support for V862 32 Channel Multi event Individual Gate QDC; support for V775 32 Channel Multievent TDC and MesyTec High resolution(11 to 13 bit) ADCs MADC-32 As the VME is an asynchronous bus, the bandwidth indicated is a theoretical limit. For VME64, It works to around 80 MB/s of Theoretical maximum bandwidth ; usually the actual transfer rate is less than 50% of the bandwidth High Readout Speeds High Density Modules can provide up to 640 Channels (1 controller + 20 Digitizers) in a single VME crate with 21 slots. Usage of high bandwidth optical interconnect link makes sure that the interconnect technology doesn t become a bottleneck while transferring of VME over CAMAC StandardChapter 2--------------------------------VME Architecture and Protocols/DS0, /DS1/DTACKDATAADDRESS/ASMASTERLWORD*D[ ]BERR*DTACK*WRITE*DS0*DS1*AS*AM[ ]IACK*BCLR*SYSRESET*ACFAIL*SLAVEBACKPLAN E INTERFACE LOGICLWORD*A[ ]D[ ]BERR*DTACK*WRITE*DS0*DS1*AS*AM[ ]IACK*SYSRESET* data TRANSFER BUS (DTB)

5 DTB ARBITRATION BUSPRIORITY INTERRUPT BUSUTILITY BUSIRQ[ ]*IRQ[ ]*A[ ]BBSY*BG[ ]IN*BR[ ]*SYSCLKBG[ ]OUT*VME ArchitectureElectrical PropertiesAll lines use TTL levels ; Low = 0 .. V; High = .. 5 VAddress, Address Modifier and data lines are active high; Protocol lines are active low.* Active low signals Addressing modes A16, A24, A32, A40, A64 The addressing mode and the access type are defined by the Address Modifier bus AM[5:0]AM Code Functions0x3BA24 block transfer0x39A24 single cycle0x2 FCR/CSR space access0x29A16 single cycle0x202eVME and 2eSST transfers (+ extended AM)0x0BA32 block transfer (BLT)0x09A32 single cycle0x08A32 64-bit block transfer (MBLT)VME Addressing Modes Address=BaseAddress + Offset The maximum VME address space is made of 264bytes (although in most cases only 232are used, since the A64 mode is very infrequent)

6 Each slave occupies a portion of this space, depending on its internal addressing capability There are 3 ways to allocate the address space of the slaves: the Base Address of the slaves which is set at hardware level by means of jumpers or rotary the position of the slave in the crate (Geographical Address) the content of some registers of the slave programmed by the software (Address Relocation)modes 2 and 3 are available in the VME64x onlyVME Address SpaceData readout is possible in following modes Single cycle Reads a word from the slave FIFO BLT/MBLT (Block Transfer/Multiplexed Block Transfer)

7 Reads a number of events limited to 256 words from any slave module In MBLT two 32 bit words are multiplexed to read as a single 64 bit word in VME64 standard CBLT (Chained Block Transfer) Most pertinent mode for nuclear physics applications allowing for event by event data Acquisition . Reads the data belonging to the same physical event from several contiguous boards in a crate limited to 256 words per CBLT cycleVME data Readout The Chained Block Transfer has been introduced for sparse data readout across multiple modules. It consists in reading the data belonging to the same physical event from several contiguous boards in a crate.

8 It uses the IACKIN IACKOUT daisy chain line already present in any VME backplane to propagate the readout token . No additional hardware nor external connections are required. The CBLT is handled by the slaves and is transparent to the master The use of the Bus Error to terminate the cycle is Block Transfer The Multi Cast Write (MCST)is a single write cycle that involves several slaves in the crate. The MCST uses the same propagation mechanism as the CBLT The master initiates the cycle like a normal single write The slaves get the data in sequence and the last one asserts the DTACKM ulti Cast Write Many VME Acquisition boards use FIFO memories to store the data .

9 This is particularly suitable for physics applications in which the events occur randomly in time and are readout sequentially A read access to any address within that range causes the non repeatable extraction of one word from the FIFO. CAEN ADC modules are endowed with 32 Events Memories The VME features a 7 level prioritized interrupt architecture; the request lines IRQ[7:1] are shared between all the slots The interrupt is initiated by the interrupter(this can be any board in any slot) that asserts one IRQ. The interrupt handlers(usually the board in slot 1) monitor the IRQ lines and generate an interrupt acknowledge cyclein response to the request The interrupt handler reads the STATUS/ID of the interrupter from the data bus If more interrupters had asserted the same IRQ line, the IACKIN IACKOUT daisy chain allows the uppermost left to respond first (priority given by the position)Interrupts in VMEC hapter 3--------------------------------Setting up a VME Acquisition systemC.

10 A . E . N . It makes possible to control the VME bus remotely from a standard PC through a high speed link The Acquisition program (DAQ) runs on the remote PC The VME board is just hardware (no software runs on it) Computing power (processors, memories, disks, etcR) is on the PC Unlike the ethernet port of a SBC, the communication link of the bus adapter must be able to sustain high data transfer rates VME PCI/PCIe: usually communicates through an optical link, requires a card inside the PCBus Adapter Feature HW and SW upgrade on PC side: you can buy a new one at any time Easy getting started: just install a driver in the PC Ready at power up (no boot required) Lower total cost of ownership Multi crate interconnection and controlused for data transferC.