VMEbus Specification Manual Third Printing INTRODUCTION

1 VMEbus Specification Manual Revision October 1 985. Third Printing INTRODUCTION . VMEbus is the most popular 16/32-bit backplane bus. Its use of the Eurocard format, its high performance, and its versatility are some of the reasons that it appeals to a wide range of users. The designer friendly and user friendly style of its Specification offers useful advice and helps ensure compatibility between VMEbus products. The following VMEbus Specification is a result of both IEEE P1014 Standard Committee and the IEC 47b Standards Committee work. The version of the VMEbus Specification presented here (Revision ) has been approved by the IEEE P1014 Standard Committee as draft It is presently undergoing the final stages of approval in both the IEEE and the IEC.

2 While the final IEEE 1014 and IEC 821 BUS standards are not expected to differ significantly from Revision , the publisher of this document does not guarantee that those standards will not differ at all. This document is being published to provide the VMEbus community with an up-to-date professional and readable document in the hope of promoting compatibility between VMEbus products and encouraging the widespread use of VMEbus . TABLE OF CONTENTS. CHAPTER 1 INTRODUCTION TO THE VMEbus Specification . VMEbus Specification OBJECTIVES. VMEbus INTERFACE SYSTEM ELEMENTS. Basic Definitions Terms Used To Describe The VMEbus Mechanical Structure Terms Used To Describe The VMEbus Functional Structure Types Of Cycles On The VMEbus Basic VMEbus Structure VMEbus Specification DIAGRAMS.

3 Specification TERMINOLOGY. Signal Line States Use Of The Asterisk (*). PROTOCOL Specification . interlocked Bus Signals Broadcast Bus Signal SYSTEM EXAMPLES AND EXPLANATIONS. CHAPTER 2 DATA TRANSFER BUS. INTRODUCTION . DATA TRANSFER BUS LINES. Addressing Lines Address Modifier Lines Data Lines Data Transfer Bus Control Lines AS*. DSO* And DS1. 2 . DTACK*. 2 . BERR*. 5 WRITE*. DTB MODULES - BASIC DESCRIPTION. MASTER. SLAVE. BUS TIMER. LOCATION MONITOR. Addressing Modes Basic Data Transfer Capabilities Block Transfer Capabilities Read-Modify-Write Capability Unaligned Transfer Capability ADDRESS-ONLY Capability 1 Interaction Between DTB Functional Modules 2.

4 4 TYPICAL OPERATI0N. Typical Data Transfer Cycles Address Pipelining DATA TRANSFER BUS ACQUISITION. DTB TIMING RULES AND OBSERVATI0NS. CHAPTER 3 DATA TRANSFER BUS ARBITRATION. BUS ARBITRATION PHILOSOPHY. Types Of Arbitration 3. 2 ARB ITRATION BUS LINES. Bus Request And Bus Grant Lines Bus Busy Line (BBSY*). Bus Clear Line (BCLR*). FUNCTIONAL MODULES. ARBlTER. REQUESTER3. Data Transfer Bus MASTER. Release Of The DTB. Acquisition Of The DTB. 3 .3. 3. 3 Other Information TYPICAL OPERATI0N. Arbitration Of Two Different Levels Of Bus Request Arbitration Of Two Bus Requests On The Same Bus Request Line RACE CONDITIONS BETWEEN MASTER. REQUESTS AND ARBlTER GRANTS.

5 CHAPTER 4 PRIORITY INTERRUPT. INTRODUCTI0N. Single Handler Systems Distributed Systems PRIORITY INTERRUPT BUS LINES. Interrupt Request Lines Interrupt Acknowledge Line 3 interrupt Acknowledge Daisy-Chain - IACKIN*/. IACKOUT*. PRIORITY INTERRUPT BUS MODULES - BASIC. DESCRIPTION. INTERRUPT HANDLER. lNTERRUPTER. IACK DAISY-CHAIN DRIVER. Interrupt Request Handling Capabilities Interrupt Request Generation Capabilities STATUS/ID Transfer Capabilities Interrupt Request Release Capabilities interaction Between Priority Interrupt Bus Modules 4. 4 TYPICAL OPERATION. Single Handler Interrupt Operation Distributed Interrupt Operation Distributed Interrupt Systems With Seven INTERRUPT HANDLERS.

6 Distributed Interrupt Systems With Two To Six INTERRUPT HANDLERS. Example: Typical Single Handler interrupt System Operation Example: Prioritization Of Two interrupts In A. Distributed interrupt System PRIORITY INTERRUPT BUS TIMING RULES AND. OBSERVATIONS. CHAPTER 5 UTILITIES. INTRODUCTION . UTILITY BUS SIGNAL LINES. UTILITY BUS MODULES. The SYSTEM CLOCK DRIVER. The SERIAL CLOCK DRIVER. The POWER MONITOR. SYSTEM INITIALIZATION AND DIAGNOSTICS. POWER PINS. RESERVED LINES. CHAPTER 6 ELECTRICAL SPECIFICATIONS. INTRODUCTION . POWER DISTRIBUTION. DC Voltage Specifications Pin And Socket Connector Electrical Ratings ELECTRICAL SIGNAL CHARACTERISTICS. BUS DRIVING AND RECEIVING REQUIREMENTS.

7 Bus Driver Definitions Driving And Loading RULES For All VMEbus Lines Driving And Loading RULES. For High Current Three-State Lines (AS*, DSO*, DS1*). Driving And Loading RULES. For Standard Three-State Lines (A01-A31, D00-D31, AM0-AM5, IACK*, LWORD*, WRITE*). Driving And Loading RULES. For High Current Totem-Pole Lines (SERCLK, SYSCLK, BCLR*). Driving And Loading RULES. For Standard Totem-Pole Lines (BGOOUT*-BG30UT*/BGOIN*-BG3lN*, IACKOUT*/. IACKIN*). Driving And Loading RULES For Open-Collector Lines (BR0*-BR3*, BBSY*, IRQ1-IRQ7*, DTACK*, BERR*, SYSFAIL*, SYSRESET*, ACFAIL*, And IACK*). BACKPLANE SIGNAL LINE INTERCONNECTIONS. Termination Networks Characteristic Impedance Additional Information USER DEFINED SIGNALS.

8 SIGNAL LINE DRIVERS AND TERMINATI0NS. CHAPTER 7 MECHANICAL Specification . INTRODUCTI0N. 7. 2 VMEbus BOARDS. Single Height Boards Double Height Boards Board Connectors Board Assemblies Board Widths VMEbus Board Warpage, Lead Length And Component Height FRONT PANELS. Handles Front Panel Mounting Front Panel Dimensions Filler Panels Board Ejectors/Injectors BACKPLANES. Backplane Dimensional Requirements Signal Line Termination Networks ASSEMBLY OF VMEbus SUBRACKS. Subracks And Slot Widths Subrack Dimensions VMEbus BACKPLANE CONNECTORS AND VMEbus BOARD CONNECTORS. Pin Assignments For The J1/P1 Connector Pin Assignments For The J2/P2 Connector APPENDIX A GLOSSARY OF VMEbus TERMS.

9 APPENDIX B VMEbus CONNECTOR/PIN DESCRIPTION. APPENDIX C USE OF THE SERCLK AND SERDAT* LINES. CHAPTER 1. INTRODUCTION TO THE VMEbus Specification . VMEbus Specification OBJECTIVES. The VMEbus Specification defines an interfacing system used to interconnect data processing, data storage, and peripheral control devices in a closely coupled hardware configuration. The system has been conceived with the following objectives: a. To allow communication between devices on the VMEbus without disturbing the internal activities of other devices interfaced to the VMEbus . b. To specify the electrical and mechanical system characteristics required to design devices that will reliably and unambiguously communicate with other devices interfaced to the VMEbus .

10 C. To specify protocols that precisely define the interaction between the VMEbus and devices interfaced to it. d. To provide terminology and definitions that describe system protocols. e. To allow a broad range of design latitude so that the designer can optimize cost and/or performance without affecting system compatibility. f. To provide a system where performance is primarily device limited, rather than system interface limited. VMEbus INTERFACE SYSTEM ELEMENTS. Basic Definitions The VMEbus structure can be described from two points of view: its mechanical structure and its functional structure. The mechanical Specification describes the physical dimensions of subracks, backplanes, front panels, plug-in boards, etc.